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332 lines
12 KiB
332 lines
12 KiB
module matrix_kbd ( input CLK, input RESET, input FREEZE, inout [15:0] ROWS, input [7:0] COLUMNS,
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input [3:0] REPORT_ADRESS, output [7:0] REPORT_DATA, output INT, output DBG);
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//output [7:0] kbd_r0, kbd_r2, kbd_r3, kbd_r4, kbd_r5, kbd_r6, kbd_r7, output INT);
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// * - ESC (29), 7 - F1 (3A), 4 - F2 (3B), 1 - NUM_LOCK (53)
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// 0 - CAPS LOCK (39), 8 - R (15), 5 - BACKSPACE (2A), 2 - ENTER (58)
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// # - LSHIFT (E1), 9 - C (06), 6 - V (19), 3 - DELETE (4C)
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// D - LCTRL (E0), C - LALT (E2), B - SPACE (2C), A - RGUI (E7)
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parameter ONE_ROW_TIME = 12000;
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parameter ROW_STT_PROCESS_TIME = 7000;
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parameter ONE_COLUMN_PROCESS_TIME = 50;
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parameter ONE_ROW_TIME_POW = 14; // 15 - 65536 tacts or 5.46 ms, 14 - 32768 tacts or 2.73 ms, 13 - 16384 tacts or 1.36 ms,
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// 12 - 8191 tacts or 683 mks, 11 - 4096 tacts or 341 mks, 10 - 2048 tacts or 171 mks, 9 - 1024 tacts or 85 mks, 8 - 512 tacts or 43 mks,
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// 7 - 256 tacts or 21 mks, other values have no guaranties
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parameter ONE_CALC_TIME_POW = 4; // 3 - 16 tacts or 1.3 mks, 4 - 32 tacts or 2.7 mks, 5 - 64 tacts or 5.3 mks, 6 - 128 tacts or 10.7 mks
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// ONE_ROW_TIME_POW > (ONE_CALC_TIME_POW - 3); ONE_CALC_TIME_POW > 2 (if 2 or smaller, top module overrun may occur)
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parameter CHATTERING_SUPRESSION_TIME = 100;
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reg [ONE_ROW_TIME_POW:0] row_time = 0;
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reg [3:0] row_counter;
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//reg [7:0] temp;
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//reg [7:0] i;
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//reg [7:0] report [6:0]; // NO BYTE 2
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//reg [7:0] report_byte;
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reg isr;
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reg isr_internal;
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reg [15:0] ROWS_EN = 0;
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reg [15:0] ROWS_OUT = 0;
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wire [15:0] ROWS_IN;
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reg [7:0] COLUMN_SHADOW;
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// reg [7:0] kbd_code;
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wire [6:0] kbd_code;
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assign kbd_code [2:0] = row_time[10:8]; // COLUMN NUM
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assign kbd_code [6:3] = row_counter; // ROW NUM
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wire [7:0] kbd_code_hid;
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reg is_pressed;
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reg last_wr;
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reg [8:0] last_adr;
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wire [7:0] last_column;
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//reg [3:0] init_delay_cnt;
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//reg [8:0] init_ram_cnt;
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reg IS_RAM_INIT = 0;
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/*always @ (negedge CLK) begin
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COLUMN_SHADOW <= COLUMNS;
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end*/
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wire [7:0] report_data_rd;
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reg [3:0] report_adress_rd;
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reg [7:0] report_data_wr;
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wire [3:0] report_adress_wr;
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assign report_adress_wr = report_adress_rd;
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assign REPORT_DATA = report_data_rd;
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reg report_wr_en;
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ram REPORT (CLK, report_wr_en, report_adress_wr, report_data_wr, report_adress_rd, report_data_rd);
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ram RAM (CLK, last_wr, last_adr, COLUMN_SHADOW, last_adr, last_column);//module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
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reg tmr_wr_en;
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reg [7:0] tmr_to_ram;
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wire [7:0] tmr_from_ram;
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//reg [7:0] tmr_adr;
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wire [6:0] tmr_adr;
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//assign tmr_adr[6:3] = kbd_code;
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assign tmr_adr [6:3] = row_counter;
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//assign tmr_adr [2:0] = 0;
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assign tmr_adr [2:0] = row_time[10:8]; //row_time[3:1];
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ram CHATTERING_SUPRESSION_TIMERS (CLK, tmr_wr_en, tmr_adr, tmr_to_ram, tmr_adr, tmr_from_ram);
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reg is_ghost;
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always @ (negedge CLK) begin
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if (RESET == 0) begin
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isr = 0;
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isr_internal = 0;
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row_time = 0;
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row_counter = 0;
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IS_RAM_INIT = 1;
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last_adr = 500;
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report_adress_rd = 5;
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report_wr_en = 0;
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COLUMN_SHADOW = 255;
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end
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else begin
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if (FREEZE == 0) begin
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if (IS_RAM_INIT) begin
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last_wr = 1;
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tmr_wr_en = 1;
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last_adr = last_adr + 1;
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COLUMN_SHADOW = 255;
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tmr_to_ram = 0;
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row_counter = last_adr[6:3];
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row_time[10:8] = last_adr[2:0];
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report_adress_rd = report_adress_rd + 1;
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if (report_adress_rd == 0)
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report_data_wr = 10;
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else
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report_data_wr = 0;//report_adress_rd & 1;
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report_wr_en = 1;
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if (last_adr == 130) begin
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tmr_wr_en = 0;
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last_wr = 0;
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IS_RAM_INIT = 0;
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report_wr_en = 0;
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end
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end
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else begin
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if (row_time == ONE_ROW_TIME) begin
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row_time = 0;
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row_counter = row_counter + 1;
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COLUMN_SHADOW <= COLUMNS; // LATCH STATE OF THE COLUMNS IN CURRENT ROW
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//last_adr = 0;
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end
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else begin
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if (row_time == 0) begin//== ONE_ROW_TIME) begin
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last_wr = 0;
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ROWS_EN = 1 << ((row_counter+1) & 15);
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last_adr = row_counter;
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end
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row_time = row_time + 1;
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end
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if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] < 140)) begin
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// if (COLUMN_SHADOW [row_time [10:8]] == 0) begin // START OF KEY PRESS PROCESSING
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// if (row_time [7:0] == 0) // AT START OF EACH COLUMN PROCESS
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// is_ghost = 0;
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// end
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// else begin
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if (COLUMN_SHADOW [row_time [10:8]] == 0) begin
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if (row_time [7] == 0) begin
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is_ghost = 0;
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end
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else if (row_time [6:0] == 0)
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last_adr = row_counter;
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else if ((row_time [6:0] == 1) && (is_ghost == 0)) begin
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// if (last_column[row_time[10:8]] == 1) begin
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// is_pressed = 1;
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// report_adress_rd = 2; // ADRESS TO MODIFIERS
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// isr_internal = 1; // INTERNAL ISR AT NEXT TACT
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// end
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if (tmr_from_ram < CHATTERING_SUPRESSION_TIME)
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tmr_to_ram = tmr_from_ram + 1;
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else if (tmr_from_ram == CHATTERING_SUPRESSION_TIME) begin
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isr_internal = 1;
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is_pressed = 1;
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report_adress_rd = 2;
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tmr_to_ram = tmr_from_ram;
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end
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else
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tmr_to_ram = tmr_from_ram;
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end
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end
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else begin
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last_adr = row_counter;
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tmr_to_ram = 0;
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if (row_time [7:0] == 1) begin
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if (last_column[row_time[10:8]] == 0) begin
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isr_internal = 1;
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is_pressed = 0;
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report_adress_rd = 2;
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end
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end
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end
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// last_adr = row_counter;
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// if (row_time[7:0] == 128) begin
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// if (COLUMN_SHADOW[row_time[10:8]] != last_column[row_time[10:8]]) begin
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// if ((COLUMN_SHADOW[row_time[10:8]] == 0) && (last_column[row_time[10:8]] == 1)) is_pressed = 1;
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// else is_pressed = 0;
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// isr_internal = 1; // INTERNAL ISR AT NEXT TACT
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// report_adress_rd = 2; // ADRESS TO MODIFIERS
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// end
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// end
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// if (row_time[7:0] == 130)
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// tmr_wr_en = 1;
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// else if (row_time[7:0] == 132)
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// tmr_wr_en = 0;
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//
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// if (row_time[10:8] == 7) begin
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// if (row_time[7:0] == 130)
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// last_wr = 1;
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// else if (row_time[7:0] == 132)
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// last_wr = 0;
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// end
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end
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else if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] == 250)) begin
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tmr_wr_en = 1;
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if (row_time[10:8] == 7)
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last_wr = 1;
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end
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else if ((row_time[ONE_ROW_TIME_POW:11] == 0) && (row_time[7:0] == 252)) begin
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tmr_wr_en = 0;
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last_wr = 0;
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end
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// if ((row_time[ONE_ROW_TIME_POW:8] == 1/*((1<<(ONE_ROW_TIME_POW-7))-1)*/) && (row_time[4:0] == 0)) begin
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// //if (row_time[7:5] == 0) begin
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// // temp = last_column;
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// //end
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// check_column (row_time[7:5]);
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// if (row_time[7:5] == 7)
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// last_wr = 1;
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// end
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// START PACK I2C_HID REPORT
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else if ((isr_internal == 1)/* && (row_time[4:0] > 1)*/) begin
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if (report_wr_en == 1) begin
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report_wr_en = 0;
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isr_internal = 0;
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isr = 1;
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if (is_pressed)
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tmr_to_ram = tmr_to_ram + 1;
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end
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else if (kbd_code_hid == 0) // IF KEY NOT EXIST, DO NOTHING
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isr_internal = 0;
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else if (kbd_code_hid[7:3] == 5'b11100) begin // BYTE WITH MODIFIERS IS READ AT START OF ALG
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if (is_pressed)
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report_data_wr = report_data_rd | (1<<(kbd_code_hid & 8'h07));
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else
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report_data_wr = report_data_rd & (~(1<<(kbd_code_hid & 8'h07)));
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if (report_data_wr == report_data_rd) begin
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isr_internal = 0;
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if (is_pressed)
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tmr_to_ram = tmr_to_ram + 1;
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end
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else
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report_wr_en = 1;
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end
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else if (report_adress_rd == 2) // IF BUTTON IS NOT MODIFIER, SET ADRESS TO FIRST BUTTON BYTE
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report_adress_rd = 4;
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else if (report_adress_rd == 10) // IF TOO MUTCH ADRESSES SEEK, END ALG (BUTTONS ARE IN ADRESSES 4-9)
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isr_internal = 0;
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else begin
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if (is_pressed) begin
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if (report_data_rd == kbd_code_hid) begin // IF BUTTON WITH SAME CODE IS IN REPORT
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isr_internal = 0; // CLEAR INTERNAL INTERRUPT, NO EXT INTERRUPT
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tmr_to_ram = tmr_to_ram + 1;
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end
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else if (report_data_rd == 0) begin // IF FREE ADRESS FOUND
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report_data_wr = kbd_code_hid; // WRITE CODE TO THIS ADRESS
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report_wr_en = 1;
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end
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else
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report_adress_rd = report_adress_rd + 1; // IF NO FREE PLACE, CONTINUE SEEK
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end
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else begin // BUTTON RELEASED
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if (report_data_rd == kbd_code_hid) begin // IF ADRESS WITH THIS CODE FOUND
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report_data_wr = 0; // WRITE 0 TO THIS ADRESS (BTN RELEASED)
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report_wr_en = 1;
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end
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else
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report_adress_rd = report_adress_rd + 1; // IF THIS CODE NOT FOUND, CONTINUE SEEK
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end
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end
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end
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else begin// if (isr_internal == 0) begin
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report_adress_rd = REPORT_ADRESS /*- 1*/; // IF REPORT FILLING PROCESS IS ENDED, SET ADRESS FROM TOP MODULE
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isr <= 0;
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end
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end
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end
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end
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end
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task check_column;
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input [2:0] column;
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begin
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if (COLUMN_SHADOW[column] != last_column[column]) begin
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//kbd_code = row_counter*8 + column;
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if ((COLUMN_SHADOW[column] == 0) && (last_column[column] == 1)) is_pressed = 1;
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else is_pressed = 0;
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isr_internal = 1; // INTERNAL ISR AT NEXT TACT
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report_adress_rd = 2; // ADRESS TO MODIFIERS
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end
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//else kbd_code = 255;
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//temp[column] = COLUMN_SHADOW[column];
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end
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endtask
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assign INT = isr;
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SB_RAM40_4K #(
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.INIT_0(256'h0062_005D_0049_0045_0060_005A_0054_004F__0052_0000_004A_004D_0057_0058_0048_0050), // ROW 0-1
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.INIT_1(256'h0063_005E_004B_004E_0061_005B_0055_0056__0000_005C_004C_0044_005F_0059_0053_0051), // ROW 2-3
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.INIT_2(256'h0029_002B_0035_001E_0014_0004_001D_0000__00E2_0000_0000_0046_0047_0000_0000_00E6), // ROW 4-5
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.INIT_3(256'h0000_00E1_0000_0000_0000_00E1_00E5_0000__0000_0000_00E0_0000_0000_0000_00E4_0000), // ROW 6-7
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.INIT_4(256'h003E_002A_0042_0043_0000_0031_0028_002C__0034_002F_002D_0027_0013_0033_0000_0038), // ROW 8-9
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.INIT_5(256'h0000_0040_0041_0026_0012_000F_0037_0000__003F_0030_002E_0025_000C_000E_0036_0000), // ROW 10-11
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.INIT_6(256'h0000_0039_003A_001F_001A_0016_001B_0000__000B_001C_0023_0024_0018_000D_0010_0011), // ROW 12-13
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.INIT_7(256'h000A_0017_0022_0021_0015_0009_0019_0005__003D_003C_003B_0020_0008_0007_0006_0000), // ROW 14-15
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//.INIT_8(256'h0000_0000_0000_0000_002C_002A_0019_003B__0000_0000_0000_0000_00E2_0015_0006_003A), // ROW 16-17
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//.INIT_9(256'h0000_0000_0000_0000_002C_002A_0019_003B__0000_0000_0000_0000_00E2_0015_0006_003A), // ROW 18-19
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.WRITE_MODE(1),
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.READ_MODE(1)
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) kbd_codes (
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.RDATA(kbd_code_hid),
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.RADDR(kbd_code),
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.RCLK(CLK),
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.RCLKE(1'b1),
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.RE(1'b1),
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.WADDR(8'b0),
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.WCLK(1'b0),
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.WCLKE(1'b0),
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.WDATA(8'b0),
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.WE(1'b0)
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);
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SB_IO #(
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.PIN_TYPE(6'b 1010_01),
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.PULLUP(1'b 0)
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) rows_io [15:0] (
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.PACKAGE_PIN(ROWS),
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.OUTPUT_ENABLE(ROWS_EN),
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.D_OUT_0(ROWS_OUT),
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.D_IN_0(ROWS_IN)
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);
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endmodule
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