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21 lines
450 B
21 lines
450 B
module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
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reg [7:0] mem [0:255];
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reg [7:0] r_data;
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reg [7:0] w_data;
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reg [7:0] w_addr;
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reg last_we;
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initial mem[0] = 255;
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always @(posedge clk) begin
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if ((last_we == 0) && (wen == 1)) begin
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w_data = wdata;
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w_addr = addr;
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mem[w_addr] <= w_data;
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end
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r_data <= mem[addr];
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last_we = wen;
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end
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assign rdata = r_data;
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endmodule
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