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module ram(input clk, wen, input [8:0] addr, input [7:0] wdata, output [7:0] rdata);
reg [7:0] mem [0:255];
reg [7:0] r_data;
reg [7:0] w_data;
reg [7:0] w_addr;
reg last_we;
initial mem[0] = 255;
always @(posedge clk) begin
if ((last_we == 0) && (wen == 1)) begin
w_data = wdata;
w_addr = addr;
mem[w_addr] <= w_data;
end
r_data <= mem[addr];
last_we = wen;
end
assign rdata = r_data;
endmodule