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127 lines
2.5 KiB

module test_counter;
reg clk, SCL, SDA;
wire SDA_OUT, I2C_ACTIVITY, I2C_READ, ACK, WR;
wire [7:0] received_byte, byte_to_transmit;
reg [7:0] to_tx = 8'hC5;
wire [8:0] i2c_counter;
reg [8:0] i, j;
reg [8:0] data_to [4:0]/* = { 9'h98, 9'h00, 9'h23, 9'h10, 9'h98 }*/;
//reg [8:0] data_to = 9'h98;
// CREATING MODULE INSTANCE
i2c_slave i2c(clk, SCL, SDA, SDA_OUT, I2C_ACTIVITY, I2C_READ, ACK, WR, received_byte, byte_to_transmit, i2c_counter);
//module i2c_slave (input CLK,
// input SCL, /*inout SDA,*/SDA_IN, output SDA_OUT, // FOR TEST
// output IS_TRANSMISSION, output IS_READ, output IS_ACK, output WR, //output ACK_MASTER_CTRL,
// output reg [7:0] RECEIVED_BYTE, input [7:0] BYTE_TO_TRANSMIT,
// output [(MAX_I2C_TRANSACTION_EXP2-1):0] COUNTER);
// SIMULATING TACT SIGNAL
always
begin
#1 clk = ~clk;
data_to[0] = 9'hd0; // TX (ADRESS 34)
data_to[1] = 9'h00;
data_to[2] = 9'h46;
data_to[3] = 9'h10;
data_to[4] = 9'h98;
/*data_to[0] = 9'hd2; // RX (ADRESS 34)
data_to[1] = 9'h1FE;
data_to[2] = 9'h1FE;
data_to[3] = 9'h1FE;
data_to[4] = 9'h1FF;*/
end
parameter SDA_STT = 30;
parameter SCL_H = 100;
parameter SCL_L1 = 70;
parameter SCL_L2 = 30;
assign byte_to_transmit = to_tx;
initial
begin
//byte_to_transmit = 8'hC5;
clk = 0;
SCL = 1;
//SDA_CTRL = 1;
to_tx = 8'hC5;
SDA = 1;
#500 SDA = 0;
#SDA_STT SCL = 0;
for (i = 0; i < 5; i++)
begin
#200 for (j = 0; j < 9; j++)
begin
#SCL_L1 SDA = data_to[i][8-j]; // first bit start
#SCL_L2 SCL = 1; // CLOCK of first bit
#SCL_H SCL = 0;
end
end
#200 SDA = 0;
#200 SCL = 1;
#40 SDA = 1;
/*
#SCL_L1 SDA = 1; // first bit start
#SCL_L2 SCL = 1; // CLOCK of first bit
#SCL_H SCL = 0; // bit 7
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 6
#SCL_L1 SDA = 1;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 5
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 4
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 4
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 3
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 2
#SCL_L1 SDA = 0;
#SCL_L2 SCL = 1;
#SCL_H SCL = 0; // 1
*/
end
// END SIMULATION AT TIME "11500"
initial
begin
#11500 $finish;
end
// CREATING VCD FILE FOR NEXT ANALYZE
initial
begin
$dumpfile("out.vcd");
$dumpvars(0,test_counter);
end
// WATCHING SOME SIGNALS
initial
$monitor($stime,, clk,,, SCL,, SDA,, I2C_ACTIVITY);
endmodule