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64 lines
1.8 KiB
64 lines
1.8 KiB
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module uart ( input CLK, input RESET, input TX_SIGNAL, input [7:0] TX_BYTE,
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output TX_ACTIVITY, output TX_LINE);
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// CLK - INPUT CLOCK (12 MHZ FOR ICESTICK), RESET: IF RESET == 0, MODULE RESETS
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// TX_SIGNAL - SIGNAL TO START TRANSMISSION (RISING EDGE), TX_BYTE - BYTE TO TRANSMIT
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// TX_ACTIVITY = 1, IF SOME BYTE IS TRANSMITTING NOW, ELSE - 0
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// TX_LINE - LINE OF UART_TX,
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// IF BYTE IS TRANSMITTING, ATTEMPT TO TRANSMIT OTHER BYTE HAS NO EFFECT
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// MODULE WORKS AT POSEDGE
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parameter CLK_DIV = 13; // 921600
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//parameter CLK_DIV = 5000; // 2400
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//parameter CLK_DIV = 104; // 115200
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reg TX_sig_last;
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reg [3:0] tx_bit_counter;
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reg [3:0] tx_clk_counter; // MUST CONTAIN CLK DIV
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//reg [7:0] tx_data;
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reg tx_activity;
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reg tx_line;
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initial begin
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TX_sig_last = 0;
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tx_line = 1;
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end
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always @ (negedge CLK) begin
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if (RESET == 0) begin
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/*tx_data = 0;*/ //tx_clk_counter = 0;
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tx_activity = 0;
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end
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else begin
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if (tx_activity) begin
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tx_clk_counter = tx_clk_counter - 1;
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if (tx_clk_counter == 0) begin
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tx_clk_counter = CLK_DIV;
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if (tx_bit_counter == 0)
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tx_activity = 0;
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else begin
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tx_bit_counter = tx_bit_counter - 1;
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if (tx_bit_counter > 0)
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tx_line = TX_BYTE[8-tx_bit_counter];
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else
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tx_line = 1; // STOP_BIT
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end
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end
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end
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else begin
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if ((TX_SIGNAL == 1) && (TX_sig_last == 0)) begin
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//tx_data = TX_BYTE;
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tx_activity = 1;
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tx_bit_counter = 9; // NO PARITY, STOP 1 BIT
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tx_clk_counter = CLK_DIV;
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tx_line = 0; // START BIT
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end
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end
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TX_sig_last = TX_SIGNAL;
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end
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end
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assign TX_LINE = tx_line;
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assign TX_ACTIVITY = tx_activity;
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endmodule
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