Browse Source

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

Pull networking updates from David Miller:

 1) Support IPV6 RA Captive Portal Identifier, from Maciej Żenczykowski.

 2) Use bio_vec in the networking instead of custom skb_frag_t, from
    Matthew Wilcox.

 3) Make use of xmit_more in r8169 driver, from Heiner Kallweit.

 4) Add devmap_hash to xdp, from Toke Høiland-Jørgensen.

 5) Support all variants of 5750X bnxt_en chips, from Michael Chan.

 6) More RTNL avoidance work in the core and mlx5 driver, from Vlad
    Buslov.

 7) Add TCP syn cookies bpf helper, from Petar Penkov.

 8) Add 'nettest' to selftests and use it, from David Ahern.

 9) Add extack support to drop_monitor, add packet alert mode and
    support for HW drops, from Ido Schimmel.

10) Add VLAN offload to stmmac, from Jose Abreu.

11) Lots of devm_platform_ioremap_resource() conversions, from
    YueHaibing.

12) Add IONIC driver, from Shannon Nelson.

13) Several kTLS cleanups, from Jakub Kicinski.

* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1930 commits)
  mlxsw: spectrum_buffers: Add the ability to query the CPU port's shared buffer
  mlxsw: spectrum: Register CPU port with devlink
  mlxsw: spectrum_buffers: Prevent changing CPU port's configuration
  net: ena: fix incorrect update of intr_delay_resolution
  net: ena: fix retrieval of nonadaptive interrupt moderation intervals
  net: ena: fix update of interrupt moderation register
  net: ena: remove all old adaptive rx interrupt moderation code from ena_com
  net: ena: remove ena_restore_ethtool_params() and relevant fields
  net: ena: remove old adaptive interrupt moderation code from ena_netdev
  net: ena: remove code duplication in ena_com_update_nonadaptive_moderation_interval _*()
  net: ena: enable the interrupt_moderation in driver_supported_features
  net: ena: reimplement set/get_coalesce()
  net: ena: switch to dim algorithm for rx adaptive interrupt moderation
  net: ena: add intr_moder_rx_interval to struct ena_com_dev and use it
  net: phy: adin: implement Energy Detect Powerdown mode via phy-tunable
  ethtool: implement Energy Detect Powerdown support via phy-tunable
  xen-netfront: do not assume sk_buff_head list is empty in error handling
  s390/ctcm: Delete unnecessary checks before the macro call “dev_kfree_skb”
  net: ena: don't wake up tx queue when down
  drop_monitor: Better sanitize notified packets
  ...
tags/v5.4-rc1
Linus Torvalds 1 month ago
parent
commit
81160dda9a
1000 changed files with 70301 additions and 23513 deletions
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  223. 9
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      drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c
  962. 1
    12
      drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c
  963. 1
    12
      drivers/net/wireless/mediatek/mt76/trace.c
  964. 6
    16
      drivers/net/wireless/mediatek/mt76/trace.h
  965. 19
    25
      drivers/net/wireless/mediatek/mt76/tx.c
  966. 25
    35
      drivers/net/wireless/mediatek/mt76/usb.c
  967. 1
    12
      drivers/net/wireless/mediatek/mt76/usb_trace.c
  968. 7
    17
      drivers/net/wireless/mediatek/mt76/usb_trace.h
  969. 1
    12
      drivers/net/wireless/mediatek/mt76/util.c
  970. 2
    2
      drivers/net/wireless/mediatek/mt76/util.h
  971. 3
    0
      drivers/net/wireless/mediatek/mt7601u/init.c
  972. 2
    2
      drivers/net/wireless/mediatek/mt7601u/main.c
  973. 2
    2
      drivers/net/wireless/quantenna/qtnfmac/pcie/pcie.c
  974. 1
    0
      drivers/net/wireless/ralink/rt2x00/rt2800usb.c
  975. 35
    101
      drivers/net/wireless/ralink/rt2x00/rt2x00debug.c
  976. 0
    3
      drivers/net/wireless/ralink/rt2x00/rt2x00dev.c
  977. 3
    6
      drivers/net/wireless/ralink/rt2x00/rt2x00usb.c
  978. 8
    3
      drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c
  979. 2
    1
      drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
  980. 0
    27
      drivers/net/wireless/realtek/rtlwifi/base.h
  981. 1
    7
      drivers/net/wireless/realtek/rtlwifi/btcoexist/halbtcoutsrc.c
  982. 1
    1
      drivers/net/wireless/realtek/rtlwifi/debug.c
  983. 0
    17
      drivers/net/wireless/realtek/rtlwifi/efuse.c
  984. 4
    4
      drivers/net/wireless/realtek/rtlwifi/pci.c
  985. 0
    18
      drivers/net/wireless/realtek/rtlwifi/regd.c
  986. 0
    29
      drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h
  987. 4
    3
      drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c
  988. 0
    4
      drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c
  989. 131
    126
      drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c
  990. 538
    508
      drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h
  991. 0
    33
      drivers/net/wireless/realtek/rtlwifi/rtl8192ce/def.h
  992. 0
    2
      drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c
  993. 111
    127
      drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c
  994. 314
    489
      drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h
  995. 5
    21
      drivers/net/wireless/realtek/rtlwifi/rtl8192cu/mac.c
  996. 0
    2
      drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c
  997. 140
    132
      drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c
  998. 275
    254
      drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h
  999. 0
    31
      drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h
  1000. 0
    0
      drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c

+ 1
- 0
.mailmap View File

@@ -65,6 +65,7 @@ Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
<dev.kurt@vandijck-laurijssen.be> <kurt.van.dijck@eia.be>
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>

+ 1
- 1
CREDITS View File

@@ -751,7 +751,7 @@ S: Santa Cruz, California
S: USA

N: Luis Correia
E: lfcorreia@users.sf.net
E: luisfcorreia@gmail.com
D: Ralink rt2x00 WLAN driver
S: Belas, Portugal


+ 17
- 0
Documentation/ABI/testing/sysfs-kernel-btf View File

@@ -0,0 +1,17 @@
What: /sys/kernel/btf
Date: Aug 2019
KernelVersion: 5.5
Contact: bpf@vger.kernel.org
Description:
Contains BTF type information and related data for kernel and
kernel modules.

What: /sys/kernel/btf/vmlinux
Date: Aug 2019
KernelVersion: 5.5
Contact: bpf@vger.kernel.org
Description:
Read-only binary attribute exposing kernel's own BTF type
information with description of all internal kernel types. See
Documentation/bpf/btf.rst for detailed description of format
itself.

+ 0
- 1
Documentation/PCI/pci-error-recovery.rst View File

@@ -421,7 +421,6 @@ That is, the recovery API only requires that:
- drivers/net/ixgbe
- drivers/net/cxgb3
- drivers/net/s2io.c
- drivers/net/qlge

The End
-------

+ 18
- 0
Documentation/bpf/prog_flow_dissector.rst View File

@@ -26,6 +26,7 @@ The inputs are:
* ``nhoff`` - initial offset of the networking header
* ``thoff`` - initial offset of the transport header, initialized to nhoff
* ``n_proto`` - L3 protocol type, parsed out of L2 header
* ``flags`` - optional flags

Flow dissector BPF program should fill out the rest of the ``struct
bpf_flow_keys`` fields. Input arguments ``nhoff/thoff/n_proto`` should be
@@ -101,6 +102,23 @@ can be called for both cases and would have to be written carefully to
handle both cases.


Flags
=====

``flow_keys->flags`` might contain optional input flags that work as follows:

* ``BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG`` - tells BPF flow dissector to
continue parsing first fragment; the default expected behavior is that
flow dissector returns as soon as it finds out that the packet is fragmented;
used by ``eth_get_headlen`` to estimate length of all headers for GRO.
* ``BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL`` - tells BPF flow dissector to
stop parsing as soon as it reaches IPv6 flow label; used by
``___skb_get_hash`` and ``__skb_get_hash_symmetric`` to get flow hash.
* ``BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP`` - tells BPF flow dissector to stop
parsing as soon as it reaches encapsulated headers; used by routing
infrastructure.


Reference Implementation
========================


+ 0
- 2
Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt View File

@@ -9,8 +9,6 @@ Required Properties:
- "mediatek,mt7622-sgmiisys", "syscon"
- "mediatek,mt7629-sgmiisys", "syscon"
- #clock-cells: Must be 1
- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up
the capability of the target PHY.

The SGMIISYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt

+ 73
- 0
Documentation/devicetree/bindings/net/adi,adin.yaml View File

@@ -0,0 +1,73 @@
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/adi,adin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADIN1200/ADIN1300 PHY

maintainers:
- Alexandru Ardelean <alexandru.ardelean@analog.com>

description: |
Bindings for Analog Devices Industrial Ethernet PHYs

allOf:
- $ref: ethernet-phy.yaml#

properties:
adi,rx-internal-delay-ps:
description: |
RGMII RX Clock Delay used only when PHY operates in RGMII mode with
internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
enum: [ 1600, 1800, 2000, 2200, 2400 ]
default: 2000

adi,tx-internal-delay-ps:
description: |
RGMII TX Clock Delay used only when PHY operates in RGMII mode with
internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
enum: [ 1600, 1800, 2000, 2200, 2400 ]
default: 2000

adi,fifo-depth-bits:
description: |
When operating in RMII mode, this option configures the FIFO depth.
enum: [ 4, 8, 12, 16, 20, 24 ]
default: 8

adi,disable-energy-detect:
description: |
Disables Energy Detect Powerdown Mode (default disabled, i.e energy detect
is enabled if this property is unspecified)
type: boolean

examples:
- |
ethernet {
#address-cells = <1>;
#size-cells = <0>;

phy-mode = "rgmii-id";

ethernet-phy@0 {
reg = <0>;

adi,rx-internal-delay-ps = <1800>;
adi,tx-internal-delay-ps = <2200>;
};
};
- |
ethernet {
#address-cells = <1>;
#size-cells = <0>;

phy-mode = "rmii";

ethernet-phy@1 {
reg = <1>;

adi,fifo-depth-bits = <16>;
adi,disable-energy-detect;
};
};

+ 3
- 0
Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml View File

@@ -17,6 +17,9 @@ properties:
compatible:
const: allwinner,sun7i-a20-gmac

reg:
maxItems: 1

interrupts:
maxItems: 1


+ 113
- 0
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml View File

@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson DWMAC Ethernet controller

maintainers:
- Neil Armstrong <narmstrong@baylibre.com>
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
properties:
compatible:
contains:
enum:
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
required:
- compatible

allOf:
- $ref: "snps,dwmac.yaml#"
- if:
properties:
compatible:
contains:
enum:
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac

then:
properties:
clocks:
items:
- description: GMAC main clock
- description: First parent clock of the internal mux
- description: Second parent clock of the internal mux

clock-names:
minItems: 3
maxItems: 3
items:
- const: stmmaceth
- const: clkin0
- const: clkin1

amlogic,tx-delay-ns:
$ref: /schemas/types.yaml#definitions/uint32
description:
The internal RGMII TX clock delay (provided by this driver) in
nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
When phy-mode is set to "rgmii" then the TX delay should be
explicitly configured. When not configured a fallback of 2ns is
used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
the TX clock delay is already provided by the PHY. In that case
this property should be set to 0ns (which disables the TX clock
delay in the MAC to prevent the clock from going off because both
PHY and MAC are adding a delay).
Any configuration is ignored when the phy-mode is set to "rmii".

properties:
compatible:
additionalItems: true
maxItems: 3
items:
- enum:
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
contains:
enum:
- snps,dwmac-3.70a
- snps,dwmac

reg:
items:
- description:
The first register range should be the one of the DWMAC controller
- description:
The second range is is for the Amlogic specific configuration
(for example the PRG_ETHERNET register range on Meson8b and newer)

required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- phy-mode

examples:
- |
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
interrupts = <8>;
interrupt-names = "macirq";
clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
};

+ 45
- 0
Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml View File

@@ -0,0 +1,45 @@
# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/aspeed,ast2600-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2600 MDIO Controller

maintainers:
- Andrew Jeffery <andrew@aj.id.au>

description: |+
The ASPEED AST2600 MDIO controller is the third iteration of ASPEED's MDIO
bus register interface, this time also separating out the controller from the
MAC.

allOf:
- $ref: "mdio.yaml#"

properties:
compatible:
const: aspeed,ast2600-mdio
reg:
maxItems: 1
description: The register range of the MDIO controller instance

required:
- compatible
- reg
- "#address-cells"
- "#size-cells"

examples:
- |
mdio0: mdio@1e650000 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650000 0x8>;
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};

+ 1
- 0
Documentation/devicetree/bindings/net/broadcom-bluetooth.txt View File

@@ -13,6 +13,7 @@ Required properties:
* "brcm,bcm20702a1"
* "brcm,bcm4330-bt"
* "brcm,bcm43438-bt"
* "brcm,bcm4345c5"

Optional properties:


+ 10
- 0
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt View File

@@ -32,6 +32,15 @@ Optional properties:
ack_gpr is the gpr register offset of CAN stop acknowledge.
ack_bit is the bit offset of CAN stop acknowledge.

- fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE).
It's SoC Implementation dependent. Refer to RM for detailed
definition. If this property is not set in device tree node
then driver selects clock source 1 by default.
0: clock source 0 (oscillator clock)
1: clock source 1 (peripheral clock)

- wakeup-source: enable CAN remote wakeup

Example:

can@1c000 {
@@ -40,4 +49,5 @@ Example:
interrupts = <48 0x2>;
interrupt-parent = <&mpic>;
clock-frequency = <200000000>; // filled in by bootloader
fsl,clk-source = <0>; // select clock source 0 for PE
};

+ 40
- 0
Documentation/devicetree/bindings/net/can/tcan4x5x.txt View File

@@ -0,0 +1,40 @@
Texas Instruments TCAN4x5x CAN Controller
================================================

This file provides device node information for the TCAN4x5x interface contains.

Required properties:
- compatible: "ti,tcan4x5x"
- reg: 0
- #address-cells: 1
- #size-cells: 0
- spi-max-frequency: Maximum frequency of the SPI bus the chip can
operate at should be less than or equal to 18 MHz.
- device-wake-gpios: Wake up GPIO to wake up the TCAN device.
- interrupt-parent: the phandle to the interrupt controller which provides
the interrupt.
- interrupts: interrupt specification for data-ready.

See Documentation/devicetree/bindings/net/can/m_can.txt for additional
required property details.

Optional properties:
- reset-gpios: Hardwired output GPIO. If not defined then software
reset.
- device-state-gpios: Input GPIO that indicates if the device is in
a sleep state or if the device is active.

Example:
tcan4x5x: tcan4x5x@0 {
compatible = "ti,tcan4x5x";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <10000000>;
bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
interrupt-parent = <&gpio1>;
interrupts = <14 GPIO_ACTIVE_LOW>;
device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
};

+ 3
- 0
Documentation/devicetree/bindings/net/dsa/ksz.txt View File

@@ -5,6 +5,9 @@ Required properties:

- compatible: For external switch chips, compatible string must be exactly one
of the following:
- "microchip,ksz8765"
- "microchip,ksz8794"
- "microchip,ksz8795"
- "microchip,ksz9477"
- "microchip,ksz9897"
- "microchip,ksz9896"

+ 1
- 1
Documentation/devicetree/bindings/net/dsa/marvell.txt View File

@@ -22,7 +22,7 @@ which is at a different MDIO base address in different switch families.
- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
6190, 6190X, 6191, 6290, 6390, 6390X
- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
6250
6220, 6250

Required properties:
- compatible : Should be one of "marvell,mv88e6085",

+ 214
- 0
Documentation/devicetree/bindings/net/dsa/mt7530.txt View File

@@ -35,6 +35,42 @@ Required properties for the child nodes within ports container:
- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
"cpu".

Port 5 of the switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
connected to external component!

Port 5 modes/configurations:
1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
GMAC of the SOC.
In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
and RGMII delay.
3. Port 5 is muxed to GMAC5 and can interface to an external phy.
Port 5 becomes an extra switch port.
Only works on platform where external phy TX<->RX lines are swapped.
Like in the Ubiquiti ER-X-SFP.
4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
Currently a 2nd CPU port is not supported by DSA code.

Depending on how the external PHY is wired:
1. normal: The PHY can only connect to 2nd GMAC but not to the switch
2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
a ethernet port. But can't interface to the 2nd GMAC.

Based on the DT the port 5 mode is configured.

Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
phy-mode must be set, see also example 2 below!
* mt7621: phy-mode = "rgmii-txid";
* mt7623: phy-mode = "rgmii";

See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required, optional properties and how the integrated switch subnodes must
be specified.
@@ -94,3 +130,181 @@ Example:
};
};
};

Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.

&eth {
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "rgmii";

fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};

gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "rgmii-txid";
phy-handle = <&phy4>;
};

mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;

/* Internal phy */
phy4: ethernet-phy@4 {
reg = <4>;
};

mt7530: switch@1f {
compatible = "mediatek,mt7621";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1f>;
pinctrl-names = "default";
mediatek,mcm;

resets = <&rstctrl 2>;
reset-names = "mcm";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
label = "lan0";
};

port@1 {
reg = <1>;
label = "lan1";
};

port@2 {
reg = <2>;
label = "lan2";
};

port@3 {
reg = <3>;
label = "lan3";
};

/* Commented out. Port 4 is handled by 2nd GMAC.
port@4 {
reg = <4>;
label = "lan4";
};
*/

cpu_port0: port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";

fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};

Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.

&eth {
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "rgmii";

fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};

mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;

/* External phy */
ephy5: ethernet-phy@7 {
reg = <7>;
};

mt7530: switch@1f {
compatible = "mediatek,mt7621";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1f>;
pinctrl-names = "default";
mediatek,mcm;

resets = <&rstctrl 2>;
reset-names = "mcm";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
label = "lan0";
};

port@1 {
reg = <1>;
label = "lan1";
};

port@2 {
reg = <2>;
label = "lan2";
};

port@3 {
reg = <3>;
label = "lan3";
};

port@4 {
reg = <4>;
label = "lan4";
};

port@5 {
reg = <5>;
label = "lan5";
phy-mode = "rgmii";
phy-handle = <&ephy5>;
};

cpu_port0: port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";

fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
};
};
};

+ 39
- 3
Documentation/devicetree/bindings/net/fsl-enetc.txt View File

@@ -11,7 +11,9 @@ Required properties:
to parent node bindings.
- compatible : Should be "fsl,enetc".

1) The ENETC external port is connected to a MDIO configurable phy:
1. The ENETC external port is connected to a MDIO configurable phy

1.1. Using the local ENETC Port MDIO interface

In this case, the ENETC node should include a "mdio" sub-node
that in turn should contain the "ethernet-phy" node describing the
@@ -47,8 +49,42 @@ Example:
};
};

2) The ENETC port is an internal port or has a fixed-link external
connection:
1.2. Using the central MDIO PCIe endpoint device

In this case, the mdio node should be defined as another PCIe
endpoint node, at the same level with the ENETC port nodes.

Required properties:

- reg : Specifies PCIe Device Number and Function
Number of the ENETC endpoint device, according
to parent node bindings.
- compatible : Should be "fsl,enetc-mdio".

The remaining required mdio bus properties are standard, their bindings
already defined in Documentation/devicetree/bindings/net/mdio.txt.

Example:

ethernet@0,0 {
compatible = "fsl,enetc";
reg = <0x000000 0 0 0 0>;
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";
};

mdio@0,3 {
compatible = "fsl,enetc-mdio";
reg = <0x000300 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
};

2. The ENETC port is an internal port or has a fixed-link external
connection

In this case, the ENETC port node defines a fixed link connection,
as specified by Documentation/devicetree/bindings/net/fixed-link.txt.

+ 1
- 0
Documentation/devicetree/bindings/net/mediatek-net.txt View File

@@ -12,6 +12,7 @@ Required properties:
"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
"mediatek,mt7622-eth": for MT7622 SoC
"mediatek,mt7629-eth": for MT7629 SoC
"ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
order. These are fe_int0, fe_int1 and fe_int2.

+ 0
- 71
Documentation/devicetree/bindings/net/meson-dwmac.txt View File

@@ -1,71 +0,0 @@
* Amlogic Meson DWMAC Ethernet controller

The device inherits all the properties of the dwmac/stmmac devices
described in the file stmmac.txt in the current directory with the
following changes.

Required properties on all platforms:

- compatible: Depending on the platform this should be one of:
- "amlogic,meson6-dwmac"
- "amlogic,meson8b-dwmac"
- "amlogic,meson8m2-dwmac"
- "amlogic,meson-gxbb-dwmac"
- "amlogic,meson-axg-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.

- reg: The first register range should be the one of the DWMAC
controller. The second range is is for the Amlogic specific
configuration (for example the PRG_ETHERNET register range
on Meson8b and newer)

Required properties on Meson8b, Meson8m2, GXBB and newer:
- clock-names: Should contain the following:
- "stmmaceth" - see stmmac.txt
- "clkin0" - first parent clock of the internal mux
- "clkin1" - second parent clock of the internal mux

Optional properties on Meson8b, Meson8m2, GXBB and newer:
- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
by this driver) in nanoseconds. Allowed values
are: 0ns, 2ns, 4ns, 6ns.
When phy-mode is set to "rgmii" then the TX
delay should be explicitly configured. When
not configured a fallback of 2ns is used.
When the phy-mode is set to either "rgmii-id"
or "rgmii-txid" the TX clock delay is already
provided by the PHY. In that case this
property should be set to 0ns (which disables
the TX clock delay in the MAC to prevent the
clock from going off because both PHY and MAC
are adding a delay).
Any configuration is ignored when the phy-mode
is set to "rmii".

Example for Meson6:

ethmac: ethernet@c9410000 {
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
0xc1108108 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&clk81>;
clock-names = "stmmaceth";
}

Example for GXBB:
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000>,
<0x0 0xc8834540 0x0 0x8>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
};

+ 12
- 8
Documentation/devicetree/bindings/net/mscc-ocelot.txt View File

@@ -12,13 +12,15 @@ Required properties:
- "sys"
- "rew"
- "qs"
- "ptp" (optional due to backward compatibility)
- "qsys"
- "ana"
- "portX" with X from 0 to the number of last port index available on that
switch
- interrupts: Should contain the switch interrupts for frame extraction and
frame injection
- interrupt-names: should contain the interrupt names: "xtr", "inj"
- interrupts: Should contain the switch interrupts for frame extraction,
frame injection and PTP ready.
- interrupt-names: should contain the interrupt names: "xtr", "inj". Can contain
"ptp_rdy" which is optional due to backward compatibility.
- ethernet-ports: A container for child nodes representing switch ports.

The ethernet-ports container has the following properties
@@ -44,6 +46,7 @@ Example:
reg = <0x1010000 0x10000>,
<0x1030000 0x10000>,
<0x1080000 0x100>,
<0x10e0000 0x10000>,
<0x11e0000 0x100>,
<0x11f0000 0x100>,
<0x1200000 0x100>,
@@ -57,11 +60,12 @@ Example:
<0x1280000 0x100>,
<0x1800000 0x80000>,
<0x1880000 0x10000>;
reg-names = "sys", "rew", "qs", "port0", "port1", "port2",
"port3", "port4", "port5", "port6", "port7",
"port8", "port9", "port10", "qsys", "ana";
interrupts = <21 22>;
interrupt-names = "xtr", "inj";
reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
"port2", "port3", "port4", "port5", "port6",
"port7", "port8", "port9", "port10", "qsys",
"ana";
interrupts = <18 21 22>;
interrupt-names = "ptp_rdy", "xtr", "inj";

ethernet-ports {
#address-cells = <1>;

+ 15
- 1
Documentation/devicetree/bindings/net/snps,dwmac.yaml View File

@@ -50,6 +50,11 @@ properties:
- allwinner,sun8i-r40-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
- snps,dwmac
- snps,dwmac-3.50a
- snps,dwmac-3.610
@@ -61,7 +66,8 @@ properties:
- snps,dwxgmac-2.10

reg:
maxItems: 1
minItems: 1
maxItems: 2

interrupts:
minItems: 1
@@ -106,6 +112,14 @@ properties:
reset-names:
const: stmmaceth

mac-mode:
maxItems: 1
description:
The property is identical to 'phy-mode', and assumes that there is mode
converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
can be passive (no SW requirement), and requires that the MAC operate
in a different mode than the PHY in order to function.

snps,axi-config:
$ref: /schemas/types.yaml#definitions/phandle
description:

+ 4
- 0
Documentation/devicetree/bindings/net/ti,dp83867.txt View File

@@ -37,6 +37,10 @@ Optional property:
for applicable values. The CLK_OUT pin can also
be disabled by this property. When omitted, the
PHY's default will be left as is.
- ti,sgmii-ref-clock-output-enable - This denotes which
SGMII configuration is used (4 or 6-wire modes).
Some MACs work with differential SGMII clock.
See data manual for details.

Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance

+ 6
- 4
Documentation/networking/af_xdp.rst View File

@@ -153,10 +153,12 @@ an example, if the UMEM is 64k and each chunk is 4k, then the UMEM has

Frames passed to the kernel are used for the ingress path (RX rings).

The user application produces UMEM addrs to this ring. Note that the
kernel will mask the incoming addr. E.g. for a chunk size of 2k, the
log2(2048) LSB of the addr will be masked off, meaning that 2048, 2050
and 3000 refers to the same chunk.
The user application produces UMEM addrs to this ring. Note that, if
running the application with aligned chunk mode, the kernel will mask
the incoming addr. E.g. for a chunk size of 2k, the log2(2048) LSB of
the addr will be masked off, meaning that 2048, 2050 and 3000 refers
to the same chunk. If the user application is run in the unaligned
chunks mode, then the incoming addr will be left untouched.


UMEM Completion Ring

+ 1
- 0
Documentation/networking/device_drivers/index.rst View File

@@ -23,6 +23,7 @@ Contents:
intel/ice
google/gve
mellanox/mlx5
pensando/ionic

.. only:: subproject and html


+ 82
- 33
Documentation/networking/device_drivers/intel/iavf.rst View File

@@ -10,11 +10,15 @@ Copyright(c) 2013-2018 Intel Corporation.
Contents
========

- Overview
- Identifying Your Adapter
- Additional Configurations
- Known Issues/Troubleshooting
- Support

Overview
========

This file describes the iavf Linux* Base Driver. This driver was formerly
called i40evf.

@@ -27,6 +31,7 @@ The guest OS loading the iavf driver must support MSI-X interrupts.

Identifying Your Adapter
========================

The driver in this kernel is compatible with devices based on the following:
* Intel(R) XL710 X710 Virtual Function
* Intel(R) X722 Virtual Function
@@ -50,9 +55,10 @@ Link messages will not be displayed to the console if the distribution is
restricting system messages. In order to see network driver link messages on
your console, set dmesg to eight by entering the following::

dmesg -n 8
# dmesg -n 8

NOTE: This setting is not saved across reboots.
NOTE:
This setting is not saved across reboots.

ethtool
-------
@@ -72,11 +78,11 @@ then requests from that VF to set VLAN tag stripping will be ignored.
To enable/disable VLAN tag stripping for a VF, issue the following command
from inside the VM in which you are running the VF::

ethtool -K <if_name> rxvlan on/off
# ethtool -K <if_name> rxvlan on/off

or alternatively::

ethtool --offload <if_name> rxvlan on/off
# ethtool --offload <if_name> rxvlan on/off

Adaptive Virtual Function
-------------------------
@@ -91,21 +97,21 @@ additional features depending on what features are available in the PF with
which the AVF is associated. The following are base mode features:

- 4 Queue Pairs (QP) and associated Configuration Status Registers (CSRs)
for Tx/Rx.
- i40e descriptors and ring format.
- Descriptor write-back completion.
- 1 control queue, with i40e descriptors, CSRs and ring format.
- 5 MSI-X interrupt vectors and corresponding i40e CSRs.
- 1 Interrupt Throttle Rate (ITR) index.