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tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store

This instruction raises #GP, aka SIGSEGV, if the effective address
is not aligned to 16-bytes.

We have assertions in tcg-op-gvec.c that the offset from ENV is
aligned, for vector types <= V128.  But the offset itself does not
validate that the final pointer is aligned -- one must also remember
to use the QEMU_ALIGNED() attribute on the vector member within ENV.

PowerPC Altivec has vector load/store instructions that silently
discard the low 4 bits of the address, making alignment mistakes
difficult to discover.  Aid that by making the most popular host
visibly signal the error.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 4 weeks ago
parent
commit
11e2bfef79
1 changed files with 22 additions and 2 deletions
  1. 22
    2
      tcg/i386/tcg-target.inc.c

+ 22
- 2
tcg/i386/tcg-target.inc.c View File

@@ -1082,14 +1082,24 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1082 1082
         }
1083 1083
         /* FALLTHRU */
1084 1084
     case TCG_TYPE_V64:
1085
+        /* There is no instruction that can validate 8-byte alignment.  */
1085 1086
         tcg_debug_assert(ret >= 16);
1086 1087
         tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
1087 1088
         break;
1088 1089
     case TCG_TYPE_V128:
1090
+        /*
1091
+         * The gvec infrastructure is asserts that v128 vector loads
1092
+         * and stores use a 16-byte aligned offset.  Validate that the
1093
+         * final pointer is aligned by using an insn that will SIGSEGV.
1094
+         */
1089 1095
         tcg_debug_assert(ret >= 16);
1090
-        tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2);
1096
+        tcg_out_vex_modrm_offset(s, OPC_MOVDQA_VxWx, ret, 0, arg1, arg2);
1091 1097
         break;
1092 1098
     case TCG_TYPE_V256:
1099
+        /*
1100
+         * The gvec infrastructure only requires 16-byte alignment,
1101
+         * so here we must use an unaligned load.
1102
+         */
1093 1103
         tcg_debug_assert(ret >= 16);
1094 1104
         tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
1095 1105
                                  ret, 0, arg1, arg2);
@@ -1117,14 +1127,24 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1117 1127
         }
1118 1128
         /* FALLTHRU */
1119 1129
     case TCG_TYPE_V64:
1130
+        /* There is no instruction that can validate 8-byte alignment.  */
1120 1131
         tcg_debug_assert(arg >= 16);
1121 1132
         tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
1122 1133
         break;
1123 1134
     case TCG_TYPE_V128:
1135
+        /*
1136
+         * The gvec infrastructure is asserts that v128 vector loads
1137
+         * and stores use a 16-byte aligned offset.  Validate that the
1138
+         * final pointer is aligned by using an insn that will SIGSEGV.
1139
+         */
1124 1140
         tcg_debug_assert(arg >= 16);
1125
-        tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2);
1141
+        tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2);
1126 1142
         break;
1127 1143
     case TCG_TYPE_V256:
1144
+        /*
1145
+         * The gvec infrastructure only requires 16-byte alignment,
1146
+         * so here we must use an unaligned store.
1147
+         */
1128 1148
         tcg_debug_assert(arg >= 16);
1129 1149
         tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
1130 1150
                                  arg, 0, arg1, arg2);

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