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tcg: Add support for vector bitwise select

This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units.  Include gvec expanders.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
master
Richard Henderson 1 month ago
parent
commit
38dc12947e
12 changed files with 86 additions and 0 deletions
  1. 14
    0
      accel/tcg/tcg-runtime-gvec.c
  2. 2
    0
      accel/tcg/tcg-runtime.h
  3. 4
    0
      tcg/README
  4. 1
    0
      tcg/aarch64/tcg-target.h
  5. 1
    0
      tcg/i386/tcg-target.h
  6. 23
    0
      tcg/tcg-op-gvec.c
  7. 7
    0
      tcg/tcg-op-gvec.h
  8. 26
    0
      tcg/tcg-op-vec.c
  9. 3
    0
      tcg/tcg-op.h
  10. 2
    0
      tcg/tcg-opc.h
  11. 2
    0
      tcg/tcg.c
  12. 1
    0
      tcg/tcg.h

+ 14
- 0
accel/tcg/tcg-runtime-gvec.c View File

@@ -1444,3 +1444,17 @@ void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc)
1444 1444
     }
1445 1445
     clear_high(d, oprsz, desc);
1446 1446
 }
1447
+
1448
+void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc)
1449
+{
1450
+    intptr_t oprsz = simd_oprsz(desc);
1451
+    intptr_t i;
1452
+
1453
+    for (i = 0; i < oprsz; i += sizeof(vec64)) {
1454
+        vec64 aa = *(vec64 *)(a + i);
1455
+        vec64 bb = *(vec64 *)(b + i);
1456
+        vec64 cc = *(vec64 *)(c + i);
1457
+        *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa);
1458
+    }
1459
+    clear_high(d, oprsz, desc);
1460
+}

+ 2
- 0
accel/tcg/tcg-runtime.h View File

@@ -303,3 +303,5 @@ DEF_HELPER_FLAGS_4(gvec_leu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
303 303
 DEF_HELPER_FLAGS_4(gvec_leu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
304 304
 DEF_HELPER_FLAGS_4(gvec_leu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
305 305
 DEF_HELPER_FLAGS_4(gvec_leu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
306
+
307
+DEF_HELPER_FLAGS_5(gvec_bitsel, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

+ 4
- 0
tcg/README View File

@@ -627,6 +627,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
627 627
 
628 628
   Compare vectors by element, storing -1 for true and 0 for false.
629 629
 
630
+* bitsel_vec v0, v1, v2, v3
631
+
632
+  Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
633
+
630 634
 *********
631 635
 
632 636
 Note 1: Some shortcuts are defined when the last operand is known to be

+ 1
- 0
tcg/aarch64/tcg-target.h View File

@@ -140,6 +140,7 @@ typedef enum {
140 140
 #define TCG_TARGET_HAS_mul_vec          1
141 141
 #define TCG_TARGET_HAS_sat_vec          1
142 142
 #define TCG_TARGET_HAS_minmax_vec       1
143
+#define TCG_TARGET_HAS_bitsel_vec       0
143 144
 
144 145
 #define TCG_TARGET_DEFAULT_MO (0)
145 146
 #define TCG_TARGET_HAS_MEMORY_BSWAP     1

+ 1
- 0
tcg/i386/tcg-target.h View File

@@ -190,6 +190,7 @@ extern bool have_avx2;
190 190
 #define TCG_TARGET_HAS_mul_vec          1
191 191
 #define TCG_TARGET_HAS_sat_vec          1
192 192
 #define TCG_TARGET_HAS_minmax_vec       1
193
+#define TCG_TARGET_HAS_bitsel_vec       0
193 194
 
194 195
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
195 196
     (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \

+ 23
- 0
tcg/tcg-op-gvec.c View File

@@ -3195,3 +3195,26 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
3195 3195
         expand_clr(dofs + oprsz, maxsz - oprsz);
3196 3196
     }
3197 3197
 }
3198
+
3199
+static void tcg_gen_bitsel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
3200
+{
3201
+    TCGv_i64 t = tcg_temp_new_i64();
3202
+
3203
+    tcg_gen_and_i64(t, b, a);
3204
+    tcg_gen_andc_i64(d, c, a);
3205
+    tcg_gen_or_i64(d, d, t);
3206
+    tcg_temp_free_i64(t);
3207
+}
3208
+
3209
+void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs,
3210
+                         uint32_t bofs, uint32_t cofs,
3211
+                         uint32_t oprsz, uint32_t maxsz)
3212
+{
3213
+    static const GVecGen4 g = {
3214
+        .fni8 = tcg_gen_bitsel_i64,
3215
+        .fniv = tcg_gen_bitsel_vec,
3216
+        .fno = gen_helper_gvec_bitsel,
3217
+    };
3218
+
3219
+    tcg_gen_gvec_4(dofs, aofs, bofs, cofs, oprsz, maxsz, &g);
3220
+}

+ 7
- 0
tcg/tcg-op-gvec.h View File

@@ -342,6 +342,13 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
342 342
                       uint32_t aofs, uint32_t bofs,
343 343
                       uint32_t oprsz, uint32_t maxsz);
344 344
 
345
+/*
346
+ * Perform vector bit select: d = (b & a) | (c & ~a).
347
+ */
348
+void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs,
349
+                         uint32_t bofs, uint32_t cofs,
350
+                         uint32_t oprsz, uint32_t maxsz);
351
+
345 352
 /*
346 353
  * 64-bit vector operations.  Use these when the register has been allocated
347 354
  * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.

+ 26
- 0
tcg/tcg-op-vec.c View File

@@ -88,6 +88,7 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
88 88
         case INDEX_op_dup2_vec:
89 89
         case INDEX_op_ld_vec:
90 90
         case INDEX_op_st_vec:
91
+        case INDEX_op_bitsel_vec:
91 92
             /* These opcodes are mandatory and should not be listed.  */
92 93
             g_assert_not_reached();
93 94
         default:
@@ -691,3 +692,28 @@ void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b)
691 692
 {
692 693
     do_shifts(vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
693 694
 }
695
+
696
+void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
697
+                        TCGv_vec b, TCGv_vec c)
698
+{
699
+    TCGTemp *rt = tcgv_vec_temp(r);
700
+    TCGTemp *at = tcgv_vec_temp(a);
701
+    TCGTemp *bt = tcgv_vec_temp(b);
702
+    TCGTemp *ct = tcgv_vec_temp(c);
703
+    TCGType type = rt->base_type;
704
+
705
+    tcg_debug_assert(at->base_type >= type);
706
+    tcg_debug_assert(bt->base_type >= type);
707
+    tcg_debug_assert(ct->base_type >= type);
708
+
709
+    if (TCG_TARGET_HAS_bitsel_vec) {
710
+        vec_gen_4(INDEX_op_bitsel_vec, type, MO_8,
711
+                  temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct));
712
+    } else {
713
+        TCGv_vec t = tcg_temp_new_vec(type);
714
+        tcg_gen_and_vec(MO_8, t, a, b);
715
+        tcg_gen_andc_vec(MO_8, r, c, a);
716
+        tcg_gen_or_vec(MO_8, r, r, t);
717
+        tcg_temp_free_vec(t);
718
+    }
719
+}

+ 3
- 0
tcg/tcg-op.h View File

@@ -1000,6 +1000,9 @@ void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
1000 1000
 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
1001 1001
                      TCGv_vec a, TCGv_vec b);
1002 1002
 
1003
+void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
1004
+                        TCGv_vec b, TCGv_vec c);
1005
+
1003 1006
 void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1004 1007
 void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1005 1008
 void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);

+ 2
- 0
tcg/tcg-opc.h View File

@@ -256,6 +256,8 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
256 256
 
257 257
 DEF(cmp_vec, 1, 2, 1, IMPLVEC)
258 258
 
259
+DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
260
+
259 261
 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
260 262
 
261 263
 #if TCG_TARGET_MAYBE_vec

+ 2
- 0
tcg/tcg.c View File

@@ -1646,6 +1646,8 @@ bool tcg_op_supported(TCGOpcode op)
1646 1646
     case INDEX_op_smax_vec:
1647 1647
     case INDEX_op_umax_vec:
1648 1648
         return have_vec && TCG_TARGET_HAS_minmax_vec;
1649
+    case INDEX_op_bitsel_vec:
1650
+        return have_vec && TCG_TARGET_HAS_bitsel_vec;
1649 1651
 
1650 1652
     default:
1651 1653
         tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);

+ 1
- 0
tcg/tcg.h View File

@@ -187,6 +187,7 @@ typedef uint64_t TCGRegSet;
187 187
 #define TCG_TARGET_HAS_mul_vec          0
188 188
 #define TCG_TARGET_HAS_sat_vec          0
189 189
 #define TCG_TARGET_HAS_minmax_vec       0
190
+#define TCG_TARGET_HAS_bitsel_vec       0
190 191
 #else
191 192
 #define TCG_TARGET_MAYBE_vec            1
192 193
 #endif

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