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dma-helpers.c 8.1KB

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  1. /*
  2. * DMA helper functions
  3. *
  4. * Copyright (c) 2009 Red Hat
  5. *
  6. * This work is licensed under the terms of the GNU General Public License
  7. * (GNU GPL), version 2 or later.
  8. */
  9. #include "qemu/osdep.h"
  10. #include "sysemu/block-backend.h"
  11. #include "sysemu/dma.h"
  12. #include "trace-root.h"
  13. #include "qemu/thread.h"
  14. #include "qemu/main-loop.h"
  15. /* #define DEBUG_IOMMU */
  16. int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len)
  17. {
  18. dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
  19. #define FILLBUF_SIZE 512
  20. uint8_t fillbuf[FILLBUF_SIZE];
  21. int l;
  22. bool error = false;
  23. memset(fillbuf, c, FILLBUF_SIZE);
  24. while (len > 0) {
  25. l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
  26. error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
  27. fillbuf, l, true);
  28. len -= l;
  29. addr += l;
  30. }
  31. return error;
  32. }
  33. void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
  34. AddressSpace *as)
  35. {
  36. qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
  37. qsg->nsg = 0;
  38. qsg->nalloc = alloc_hint;
  39. qsg->size = 0;
  40. qsg->as = as;
  41. qsg->dev = dev;
  42. object_ref(OBJECT(dev));
  43. }
  44. void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
  45. {
  46. if (qsg->nsg == qsg->nalloc) {
  47. qsg->nalloc = 2 * qsg->nalloc + 1;
  48. qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
  49. }
  50. qsg->sg[qsg->nsg].base = base;
  51. qsg->sg[qsg->nsg].len = len;
  52. qsg->size += len;
  53. ++qsg->nsg;
  54. }
  55. void qemu_sglist_destroy(QEMUSGList *qsg)
  56. {
  57. object_unref(OBJECT(qsg->dev));
  58. g_free(qsg->sg);
  59. memset(qsg, 0, sizeof(*qsg));
  60. }
  61. typedef struct {
  62. BlockAIOCB common;
  63. AioContext *ctx;
  64. BlockAIOCB *acb;
  65. QEMUSGList *sg;
  66. uint32_t align;
  67. uint64_t offset;
  68. DMADirection dir;
  69. int sg_cur_index;
  70. dma_addr_t sg_cur_byte;
  71. QEMUIOVector iov;
  72. QEMUBH *bh;
  73. DMAIOFunc *io_func;
  74. void *io_func_opaque;
  75. } DMAAIOCB;
  76. static void dma_blk_cb(void *opaque, int ret);
  77. static void reschedule_dma(void *opaque)
  78. {
  79. DMAAIOCB *dbs = (DMAAIOCB *)opaque;
  80. assert(!dbs->acb && dbs->bh);
  81. qemu_bh_delete(dbs->bh);
  82. dbs->bh = NULL;
  83. dma_blk_cb(dbs, 0);
  84. }
  85. static void dma_blk_unmap(DMAAIOCB *dbs)
  86. {
  87. int i;
  88. for (i = 0; i < dbs->iov.niov; ++i) {
  89. dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
  90. dbs->iov.iov[i].iov_len, dbs->dir,
  91. dbs->iov.iov[i].iov_len);
  92. }
  93. qemu_iovec_reset(&dbs->iov);
  94. }
  95. static void dma_complete(DMAAIOCB *dbs, int ret)
  96. {
  97. trace_dma_complete(dbs, ret, dbs->common.cb);
  98. assert(!dbs->acb && !dbs->bh);
  99. dma_blk_unmap(dbs);
  100. if (dbs->common.cb) {
  101. dbs->common.cb(dbs->common.opaque, ret);
  102. }
  103. qemu_iovec_destroy(&dbs->iov);
  104. qemu_aio_unref(dbs);
  105. }
  106. static void dma_blk_cb(void *opaque, int ret)
  107. {
  108. DMAAIOCB *dbs = (DMAAIOCB *)opaque;
  109. dma_addr_t cur_addr, cur_len;
  110. void *mem;
  111. trace_dma_blk_cb(dbs, ret);
  112. dbs->acb = NULL;
  113. dbs->offset += dbs->iov.size;
  114. if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
  115. dma_complete(dbs, ret);
  116. return;
  117. }
  118. dma_blk_unmap(dbs);
  119. while (dbs->sg_cur_index < dbs->sg->nsg) {
  120. cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
  121. cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
  122. mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir);
  123. if (!mem)
  124. break;
  125. qemu_iovec_add(&dbs->iov, mem, cur_len);
  126. dbs->sg_cur_byte += cur_len;
  127. if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
  128. dbs->sg_cur_byte = 0;
  129. ++dbs->sg_cur_index;
  130. }
  131. }
  132. if (dbs->iov.size == 0) {
  133. trace_dma_map_wait(dbs);
  134. dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
  135. cpu_register_map_client(dbs->bh);
  136. return;
  137. }
  138. if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) {
  139. qemu_iovec_discard_back(&dbs->iov,
  140. QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align));
  141. }
  142. aio_context_acquire(dbs->ctx);
  143. dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
  144. dma_blk_cb, dbs, dbs->io_func_opaque);
  145. aio_context_release(dbs->ctx);
  146. assert(dbs->acb);
  147. }
  148. static void dma_aio_cancel(BlockAIOCB *acb)
  149. {
  150. DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
  151. trace_dma_aio_cancel(dbs);
  152. assert(!(dbs->acb && dbs->bh));
  153. if (dbs->acb) {
  154. /* This will invoke dma_blk_cb. */
  155. blk_aio_cancel_async(dbs->acb);
  156. return;
  157. }
  158. if (dbs->bh) {
  159. cpu_unregister_map_client(dbs->bh);
  160. qemu_bh_delete(dbs->bh);
  161. dbs->bh = NULL;
  162. }
  163. if (dbs->common.cb) {
  164. dbs->common.cb(dbs->common.opaque, -ECANCELED);
  165. }
  166. }
  167. static AioContext *dma_get_aio_context(BlockAIOCB *acb)
  168. {
  169. DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
  170. return dbs->ctx;
  171. }
  172. static const AIOCBInfo dma_aiocb_info = {
  173. .aiocb_size = sizeof(DMAAIOCB),
  174. .cancel_async = dma_aio_cancel,
  175. .get_aio_context = dma_get_aio_context,
  176. };
  177. BlockAIOCB *dma_blk_io(AioContext *ctx,
  178. QEMUSGList *sg, uint64_t offset, uint32_t align,
  179. DMAIOFunc *io_func, void *io_func_opaque,
  180. BlockCompletionFunc *cb,
  181. void *opaque, DMADirection dir)
  182. {
  183. DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
  184. trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
  185. dbs->acb = NULL;
  186. dbs->sg = sg;
  187. dbs->ctx = ctx;
  188. dbs->offset = offset;
  189. dbs->align = align;
  190. dbs->sg_cur_index = 0;
  191. dbs->sg_cur_byte = 0;
  192. dbs->dir = dir;
  193. dbs->io_func = io_func;
  194. dbs->io_func_opaque = io_func_opaque;
  195. dbs->bh = NULL;
  196. qemu_iovec_init(&dbs->iov, sg->nsg);
  197. dma_blk_cb(dbs, 0);
  198. return &dbs->common;
  199. }
  200. static
  201. BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
  202. BlockCompletionFunc *cb, void *cb_opaque,
  203. void *opaque)
  204. {
  205. BlockBackend *blk = opaque;
  206. return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
  207. }
  208. BlockAIOCB *dma_blk_read(BlockBackend *blk,
  209. QEMUSGList *sg, uint64_t offset, uint32_t align,
  210. void (*cb)(void *opaque, int ret), void *opaque)
  211. {
  212. return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
  213. dma_blk_read_io_func, blk, cb, opaque,
  214. DMA_DIRECTION_FROM_DEVICE);
  215. }
  216. static
  217. BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
  218. BlockCompletionFunc *cb, void *cb_opaque,
  219. void *opaque)
  220. {
  221. BlockBackend *blk = opaque;
  222. return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
  223. }
  224. BlockAIOCB *dma_blk_write(BlockBackend *blk,
  225. QEMUSGList *sg, uint64_t offset, uint32_t align,
  226. void (*cb)(void *opaque, int ret), void *opaque)
  227. {
  228. return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
  229. dma_blk_write_io_func, blk, cb, opaque,
  230. DMA_DIRECTION_TO_DEVICE);
  231. }
  232. static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
  233. DMADirection dir)
  234. {
  235. uint64_t resid;
  236. int sg_cur_index;
  237. resid = sg->size;
  238. sg_cur_index = 0;
  239. len = MIN(len, resid);
  240. while (len > 0) {
  241. ScatterGatherEntry entry = sg->sg[sg_cur_index++];
  242. int32_t xfer = MIN(len, entry.len);
  243. dma_memory_rw(sg->as, entry.base, ptr, xfer, dir);
  244. ptr += xfer;
  245. len -= xfer;
  246. resid -= xfer;
  247. }
  248. return resid;
  249. }
  250. uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
  251. {
  252. return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
  253. }
  254. uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
  255. {
  256. return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
  257. }
  258. void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
  259. QEMUSGList *sg, enum BlockAcctType type)
  260. {
  261. block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
  262. }