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  1. /*
  2. * Test Server
  3. *
  4. * Copyright IBM, Corp. 2011
  5. *
  6. * Authors:
  7. * Anthony Liguori <aliguori@us.ibm.com>
  8. *
  9. * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10. * See the COPYING file in the top-level directory.
  11. *
  12. */
  13. #include "qemu/osdep.h"
  14. #include "qapi/error.h"
  15. #include "qemu-common.h"
  16. #include "cpu.h"
  17. #include "sysemu/qtest.h"
  18. #include "hw/qdev.h"
  19. #include "chardev/char-fe.h"
  20. #include "exec/ioport.h"
  21. #include "exec/memory.h"
  22. #include "hw/irq.h"
  23. #include "sysemu/accel.h"
  24. #include "sysemu/sysemu.h"
  25. #include "sysemu/cpus.h"
  26. #include "qemu/config-file.h"
  27. #include "qemu/option.h"
  28. #include "qemu/error-report.h"
  29. #include "qemu/cutils.h"
  30. #ifdef TARGET_PPC64
  31. #include "hw/ppc/spapr_rtas.h"
  32. #endif
  33. #define MAX_IRQ 256
  34. bool qtest_allowed;
  35. static DeviceState *irq_intercept_dev;
  36. static FILE *qtest_log_fp;
  37. static CharBackend qtest_chr;
  38. static GString *inbuf;
  39. static int irq_levels[MAX_IRQ];
  40. static qemu_timeval start_time;
  41. static bool qtest_opened;
  42. #define FMT_timeval "%ld.%06ld"
  43. /**
  44. * QTest Protocol
  45. *
  46. * Line based protocol, request/response based. Server can send async messages
  47. * so clients should always handle many async messages before the response
  48. * comes in.
  49. *
  50. * Valid requests
  51. *
  52. * Clock management:
  53. *
  54. * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
  55. * let you adjust the value of the clock (monotonically). All the commands
  56. * return the current value of the clock in nanoseconds.
  57. *
  58. * > clock_step
  59. * < OK VALUE
  60. *
  61. * Advance the clock to the next deadline. Useful when waiting for
  62. * asynchronous events.
  63. *
  64. * > clock_step NS
  65. * < OK VALUE
  66. *
  67. * Advance the clock by NS nanoseconds.
  68. *
  69. * > clock_set NS
  70. * < OK VALUE
  71. *
  72. * Advance the clock to NS nanoseconds (do nothing if it's already past).
  73. *
  74. * PIO and memory access:
  75. *
  76. * > outb ADDR VALUE
  77. * < OK
  78. *
  79. * > outw ADDR VALUE
  80. * < OK
  81. *
  82. * > outl ADDR VALUE
  83. * < OK
  84. *
  85. * > inb ADDR
  86. * < OK VALUE
  87. *
  88. * > inw ADDR
  89. * < OK VALUE
  90. *
  91. * > inl ADDR
  92. * < OK VALUE
  93. *
  94. * > writeb ADDR VALUE
  95. * < OK
  96. *
  97. * > writew ADDR VALUE
  98. * < OK
  99. *
  100. * > writel ADDR VALUE
  101. * < OK
  102. *
  103. * > writeq ADDR VALUE
  104. * < OK
  105. *
  106. * > readb ADDR
  107. * < OK VALUE
  108. *
  109. * > readw ADDR
  110. * < OK VALUE
  111. *
  112. * > readl ADDR
  113. * < OK VALUE
  114. *
  115. * > readq ADDR
  116. * < OK VALUE
  117. *
  118. * > read ADDR SIZE
  119. * < OK DATA
  120. *
  121. * > write ADDR SIZE DATA
  122. * < OK
  123. *
  124. * > b64read ADDR SIZE
  125. * < OK B64_DATA
  126. *
  127. * > b64write ADDR SIZE B64_DATA
  128. * < OK
  129. *
  130. * > memset ADDR SIZE VALUE
  131. * < OK
  132. *
  133. * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
  134. * For 'memset' a zero size is permitted and does nothing.
  135. *
  136. * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
  137. * than the expected size, the value will be zero filled at the end of the data
  138. * sequence.
  139. *
  140. * B64_DATA is an arbitrarily long base64 encoded string.
  141. * If the sizes do not match, the data will be truncated.
  142. *
  143. * IRQ management:
  144. *
  145. * > irq_intercept_in QOM-PATH
  146. * < OK
  147. *
  148. * > irq_intercept_out QOM-PATH
  149. * < OK
  150. *
  151. * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
  152. * QOM-PATH. When the pin is triggered, one of the following async messages
  153. * will be printed to the qtest stream:
  154. *
  155. * IRQ raise NUM
  156. * IRQ lower NUM
  157. *
  158. * where NUM is an IRQ number. For the PC, interrupts can be intercepted
  159. * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
  160. * NUM=0 even though it is remapped to GSI 2).
  161. *
  162. * Setting interrupt level:
  163. *
  164. * > set_irq_in QOM-PATH NAME NUM LEVEL
  165. * < OK
  166. *
  167. * where NAME is the name of the irq/gpio list, NUM is an IRQ number and
  168. * LEVEL is an signed integer IRQ level.
  169. *
  170. * Forcibly set the given interrupt pin to the given level.
  171. *
  172. */
  173. static int hex2nib(char ch)
  174. {
  175. if (ch >= '0' && ch <= '9') {
  176. return ch - '0';
  177. } else if (ch >= 'a' && ch <= 'f') {
  178. return 10 + (ch - 'a');
  179. } else if (ch >= 'A' && ch <= 'F') {
  180. return 10 + (ch - 'A');
  181. } else {
  182. return -1;
  183. }
  184. }
  185. static void qtest_get_time(qemu_timeval *tv)
  186. {
  187. qemu_gettimeofday(tv);
  188. tv->tv_sec -= start_time.tv_sec;
  189. tv->tv_usec -= start_time.tv_usec;
  190. if (tv->tv_usec < 0) {
  191. tv->tv_usec += 1000000;
  192. tv->tv_sec -= 1;
  193. }
  194. }
  195. static void qtest_send_prefix(CharBackend *chr)
  196. {
  197. qemu_timeval tv;
  198. if (!qtest_log_fp || !qtest_opened) {
  199. return;
  200. }
  201. qtest_get_time(&tv);
  202. fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
  203. (long) tv.tv_sec, (long) tv.tv_usec);
  204. }
  205. static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
  206. {
  207. va_list ap;
  208. if (!qtest_log_fp || !qtest_opened) {
  209. return;
  210. }
  211. qtest_send_prefix(NULL);
  212. va_start(ap, fmt);
  213. vfprintf(qtest_log_fp, fmt, ap);
  214. va_end(ap);
  215. }
  216. static void do_qtest_send(CharBackend *chr, const char *str, size_t len)
  217. {
  218. qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
  219. if (qtest_log_fp && qtest_opened) {
  220. fprintf(qtest_log_fp, "%s", str);
  221. }
  222. }
  223. static void qtest_send(CharBackend *chr, const char *str)
  224. {
  225. do_qtest_send(chr, str, strlen(str));
  226. }
  227. static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
  228. const char *fmt, ...)
  229. {
  230. va_list ap;
  231. gchar *buffer;
  232. va_start(ap, fmt);
  233. buffer = g_strdup_vprintf(fmt, ap);
  234. qtest_send(chr, buffer);
  235. g_free(buffer);
  236. va_end(ap);
  237. }
  238. static void qtest_irq_handler(void *opaque, int n, int level)
  239. {
  240. qemu_irq old_irq = *(qemu_irq *)opaque;
  241. qemu_set_irq(old_irq, level);
  242. if (irq_levels[n] != level) {
  243. CharBackend *chr = &qtest_chr;
  244. irq_levels[n] = level;
  245. qtest_send_prefix(chr);
  246. qtest_sendf(chr, "IRQ %s %d\n",
  247. level ? "raise" : "lower", n);
  248. }
  249. }
  250. static void qtest_process_command(CharBackend *chr, gchar **words)
  251. {
  252. const gchar *command;
  253. g_assert(words);
  254. command = words[0];
  255. if (qtest_log_fp) {
  256. qemu_timeval tv;
  257. int i;
  258. qtest_get_time(&tv);
  259. fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
  260. (long) tv.tv_sec, (long) tv.tv_usec);
  261. for (i = 0; words[i]; i++) {
  262. fprintf(qtest_log_fp, " %s", words[i]);
  263. }
  264. fprintf(qtest_log_fp, "\n");
  265. }
  266. g_assert(command);
  267. if (strcmp(words[0], "irq_intercept_out") == 0
  268. || strcmp(words[0], "irq_intercept_in") == 0) {
  269. DeviceState *dev;
  270. NamedGPIOList *ngl;
  271. g_assert(words[1]);
  272. dev = DEVICE(object_resolve_path(words[1], NULL));
  273. if (!dev) {
  274. qtest_send_prefix(chr);
  275. qtest_send(chr, "FAIL Unknown device\n");
  276. return;
  277. }
  278. if (irq_intercept_dev) {
  279. qtest_send_prefix(chr);
  280. if (irq_intercept_dev != dev) {
  281. qtest_send(chr, "FAIL IRQ intercept already enabled\n");
  282. } else {
  283. qtest_send(chr, "OK\n");
  284. }
  285. return;
  286. }
  287. QLIST_FOREACH(ngl, &dev->gpios, node) {
  288. /* We don't support intercept of named GPIOs yet */
  289. if (ngl->name) {
  290. continue;
  291. }
  292. if (words[0][14] == 'o') {
  293. int i;
  294. for (i = 0; i < ngl->num_out; ++i) {
  295. qemu_irq *disconnected = g_new0(qemu_irq, 1);
  296. qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
  297. disconnected, i);
  298. *disconnected = qdev_intercept_gpio_out(dev, icpt,
  299. ngl->name, i);
  300. }
  301. } else {
  302. qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
  303. ngl->num_in);
  304. }
  305. }
  306. irq_intercept_dev = dev;
  307. qtest_send_prefix(chr);
  308. qtest_send(chr, "OK\n");
  309. } else if (strcmp(words[0], "set_irq_in") == 0) {
  310. DeviceState *dev;
  311. qemu_irq irq;
  312. char *name;
  313. int ret;
  314. int num;
  315. int level;
  316. g_assert(words[1] && words[2] && words[3] && words[4]);
  317. dev = DEVICE(object_resolve_path(words[1], NULL));
  318. if (!dev) {
  319. qtest_send_prefix(chr);
  320. qtest_send(chr, "FAIL Unknown device\n");
  321. return;
  322. }
  323. if (strcmp(words[2], "unnamed-gpio-in") == 0) {
  324. name = NULL;
  325. } else {
  326. name = words[2];
  327. }
  328. ret = qemu_strtoi(words[3], NULL, 0, &num);
  329. g_assert(!ret);
  330. ret = qemu_strtoi(words[4], NULL, 0, &level);
  331. g_assert(!ret);
  332. irq = qdev_get_gpio_in_named(dev, name, num);
  333. qemu_set_irq(irq, level);
  334. qtest_send_prefix(chr);
  335. qtest_send(chr, "OK\n");
  336. } else if (strcmp(words[0], "outb") == 0 ||
  337. strcmp(words[0], "outw") == 0 ||
  338. strcmp(words[0], "outl") == 0) {
  339. unsigned long addr;
  340. unsigned long value;
  341. int ret;
  342. g_assert(words[1] && words[2]);
  343. ret = qemu_strtoul(words[1], NULL, 0, &addr);
  344. g_assert(ret == 0);
  345. ret = qemu_strtoul(words[2], NULL, 0, &value);
  346. g_assert(ret == 0);
  347. g_assert(addr <= 0xffff);
  348. if (words[0][3] == 'b') {
  349. cpu_outb(addr, value);
  350. } else if (words[0][3] == 'w') {
  351. cpu_outw(addr, value);
  352. } else if (words[0][3] == 'l') {
  353. cpu_outl(addr, value);
  354. }
  355. qtest_send_prefix(chr);
  356. qtest_send(chr, "OK\n");
  357. } else if (strcmp(words[0], "inb") == 0 ||
  358. strcmp(words[0], "inw") == 0 ||
  359. strcmp(words[0], "inl") == 0) {
  360. unsigned long addr;
  361. uint32_t value = -1U;
  362. int ret;
  363. g_assert(words[1]);
  364. ret = qemu_strtoul(words[1], NULL, 0, &addr);
  365. g_assert(ret == 0);
  366. g_assert(addr <= 0xffff);
  367. if (words[0][2] == 'b') {
  368. value = cpu_inb(addr);
  369. } else if (words[0][2] == 'w') {
  370. value = cpu_inw(addr);
  371. } else if (words[0][2] == 'l') {
  372. value = cpu_inl(addr);
  373. }
  374. qtest_send_prefix(chr);
  375. qtest_sendf(chr, "OK 0x%04x\n", value);
  376. } else if (strcmp(words[0], "writeb") == 0 ||
  377. strcmp(words[0], "writew") == 0 ||
  378. strcmp(words[0], "writel") == 0 ||
  379. strcmp(words[0], "writeq") == 0) {
  380. uint64_t addr;
  381. uint64_t value;
  382. int ret;
  383. g_assert(words[1] && words[2]);
  384. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  385. g_assert(ret == 0);
  386. ret = qemu_strtou64(words[2], NULL, 0, &value);
  387. g_assert(ret == 0);
  388. if (words[0][5] == 'b') {
  389. uint8_t data = value;
  390. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  391. &data, 1, true);
  392. } else if (words[0][5] == 'w') {
  393. uint16_t data = value;
  394. tswap16s(&data);
  395. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  396. (uint8_t *) &data, 2, true);
  397. } else if (words[0][5] == 'l') {
  398. uint32_t data = value;
  399. tswap32s(&data);
  400. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  401. (uint8_t *) &data, 4, true);
  402. } else if (words[0][5] == 'q') {
  403. uint64_t data = value;
  404. tswap64s(&data);
  405. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  406. (uint8_t *) &data, 8, true);
  407. }
  408. qtest_send_prefix(chr);
  409. qtest_send(chr, "OK\n");
  410. } else if (strcmp(words[0], "readb") == 0 ||
  411. strcmp(words[0], "readw") == 0 ||
  412. strcmp(words[0], "readl") == 0 ||
  413. strcmp(words[0], "readq") == 0) {
  414. uint64_t addr;
  415. uint64_t value = UINT64_C(-1);
  416. int ret;
  417. g_assert(words[1]);
  418. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  419. g_assert(ret == 0);
  420. if (words[0][4] == 'b') {
  421. uint8_t data;
  422. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  423. &data, 1, false);
  424. value = data;
  425. } else if (words[0][4] == 'w') {
  426. uint16_t data;
  427. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  428. (uint8_t *) &data, 2, false);
  429. value = tswap16(data);
  430. } else if (words[0][4] == 'l') {
  431. uint32_t data;
  432. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  433. (uint8_t *) &data, 4, false);
  434. value = tswap32(data);
  435. } else if (words[0][4] == 'q') {
  436. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  437. (uint8_t *) &value, 8, false);
  438. tswap64s(&value);
  439. }
  440. qtest_send_prefix(chr);
  441. qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
  442. } else if (strcmp(words[0], "read") == 0) {
  443. uint64_t addr, len, i;
  444. uint8_t *data;
  445. char *enc;
  446. int ret;
  447. g_assert(words[1] && words[2]);
  448. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  449. g_assert(ret == 0);
  450. ret = qemu_strtou64(words[2], NULL, 0, &len);
  451. g_assert(ret == 0);
  452. /* We'd send garbage to libqtest if len is 0 */
  453. g_assert(len);
  454. data = g_malloc(len);
  455. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  456. data, len, false);
  457. enc = g_malloc(2 * len + 1);
  458. for (i = 0; i < len; i++) {
  459. sprintf(&enc[i * 2], "%02x", data[i]);
  460. }
  461. qtest_send_prefix(chr);
  462. qtest_sendf(chr, "OK 0x%s\n", enc);
  463. g_free(data);
  464. g_free(enc);
  465. } else if (strcmp(words[0], "b64read") == 0) {
  466. uint64_t addr, len;
  467. uint8_t *data;
  468. gchar *b64_data;
  469. int ret;
  470. g_assert(words[1] && words[2]);
  471. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  472. g_assert(ret == 0);
  473. ret = qemu_strtou64(words[2], NULL, 0, &len);
  474. g_assert(ret == 0);
  475. data = g_malloc(len);
  476. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  477. data, len, false);
  478. b64_data = g_base64_encode(data, len);
  479. qtest_send_prefix(chr);
  480. qtest_sendf(chr, "OK %s\n", b64_data);
  481. g_free(data);
  482. g_free(b64_data);
  483. } else if (strcmp(words[0], "write") == 0) {
  484. uint64_t addr, len, i;
  485. uint8_t *data;
  486. size_t data_len;
  487. int ret;
  488. g_assert(words[1] && words[2] && words[3]);
  489. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  490. g_assert(ret == 0);
  491. ret = qemu_strtou64(words[2], NULL, 0, &len);
  492. g_assert(ret == 0);
  493. data_len = strlen(words[3]);
  494. if (data_len < 3) {
  495. qtest_send(chr, "ERR invalid argument size\n");
  496. return;
  497. }
  498. data = g_malloc(len);
  499. for (i = 0; i < len; i++) {
  500. if ((i * 2 + 4) <= data_len) {
  501. data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
  502. data[i] |= hex2nib(words[3][i * 2 + 3]);
  503. } else {
  504. data[i] = 0;
  505. }
  506. }
  507. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  508. data, len, true);
  509. g_free(data);
  510. qtest_send_prefix(chr);
  511. qtest_send(chr, "OK\n");
  512. } else if (strcmp(words[0], "memset") == 0) {
  513. uint64_t addr, len;
  514. uint8_t *data;
  515. unsigned long pattern;
  516. int ret;
  517. g_assert(words[1] && words[2] && words[3]);
  518. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  519. g_assert(ret == 0);
  520. ret = qemu_strtou64(words[2], NULL, 0, &len);
  521. g_assert(ret == 0);
  522. ret = qemu_strtoul(words[3], NULL, 0, &pattern);
  523. g_assert(ret == 0);
  524. if (len) {
  525. data = g_malloc(len);
  526. memset(data, pattern, len);
  527. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  528. data, len, true);
  529. g_free(data);
  530. }
  531. qtest_send_prefix(chr);
  532. qtest_send(chr, "OK\n");
  533. } else if (strcmp(words[0], "b64write") == 0) {
  534. uint64_t addr, len;
  535. uint8_t *data;
  536. size_t data_len;
  537. gsize out_len;
  538. int ret;
  539. g_assert(words[1] && words[2] && words[3]);
  540. ret = qemu_strtou64(words[1], NULL, 0, &addr);
  541. g_assert(ret == 0);
  542. ret = qemu_strtou64(words[2], NULL, 0, &len);
  543. g_assert(ret == 0);
  544. data_len = strlen(words[3]);
  545. if (data_len < 3) {
  546. qtest_send(chr, "ERR invalid argument size\n");
  547. return;
  548. }
  549. data = g_base64_decode_inplace(words[3], &out_len);
  550. if (out_len != len) {
  551. qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
  552. "found %zu)\n",
  553. len, out_len);
  554. out_len = MIN(out_len, len);
  555. }
  556. address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
  557. data, len, true);
  558. qtest_send_prefix(chr);
  559. qtest_send(chr, "OK\n");
  560. } else if (strcmp(words[0], "endianness") == 0) {
  561. qtest_send_prefix(chr);
  562. #if defined(TARGET_WORDS_BIGENDIAN)
  563. qtest_sendf(chr, "OK big\n");
  564. #else
  565. qtest_sendf(chr, "OK little\n");
  566. #endif
  567. #ifdef TARGET_PPC64
  568. } else if (strcmp(words[0], "rtas") == 0) {
  569. uint64_t res, args, ret;
  570. unsigned long nargs, nret;
  571. int rc;
  572. rc = qemu_strtoul(words[2], NULL, 0, &nargs);
  573. g_assert(rc == 0);
  574. rc = qemu_strtou64(words[3], NULL, 0, &args);
  575. g_assert(rc == 0);
  576. rc = qemu_strtoul(words[4], NULL, 0, &nret);
  577. g_assert(rc == 0);
  578. rc = qemu_strtou64(words[5], NULL, 0, &ret);
  579. g_assert(rc == 0);
  580. res = qtest_rtas_call(words[1], nargs, args, nret, ret);
  581. qtest_send_prefix(chr);
  582. qtest_sendf(chr, "OK %"PRIu64"\n", res);
  583. #endif
  584. } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
  585. int64_t ns;
  586. if (words[1]) {
  587. int ret = qemu_strtoi64(words[1], NULL, 0, &ns);
  588. g_assert(ret == 0);
  589. } else {
  590. ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
  591. }
  592. qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
  593. qtest_send_prefix(chr);
  594. qtest_sendf(chr, "OK %"PRIi64"\n",
  595. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  596. } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
  597. int64_t ns;
  598. int ret;
  599. g_assert(words[1]);
  600. ret = qemu_strtoi64(words[1], NULL, 0, &ns);
  601. g_assert(ret == 0);
  602. qtest_clock_warp(ns);
  603. qtest_send_prefix(chr);
  604. qtest_sendf(chr, "OK %"PRIi64"\n",
  605. (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
  606. } else {
  607. qtest_send_prefix(chr);
  608. qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
  609. }
  610. }
  611. static void qtest_process_inbuf(CharBackend *chr, GString *inbuf)
  612. {
  613. char *end;
  614. while ((end = strchr(inbuf->str, '\n')) != NULL) {
  615. size_t offset;
  616. GString *cmd;
  617. gchar **words;
  618. offset = end - inbuf->str;
  619. cmd = g_string_new_len(inbuf->str, offset);
  620. g_string_erase(inbuf, 0, offset + 1);
  621. words = g_strsplit(cmd->str, " ", 0);
  622. qtest_process_command(chr, words);
  623. g_strfreev(words);
  624. g_string_free(cmd, TRUE);
  625. }
  626. }
  627. static void qtest_read(void *opaque, const uint8_t *buf, int size)
  628. {
  629. CharBackend *chr = opaque;
  630. g_string_append_len(inbuf, (const gchar *)buf, size);
  631. qtest_process_inbuf(chr, inbuf);
  632. }
  633. static int qtest_can_read(void *opaque)
  634. {
  635. return 1024;
  636. }
  637. static void qtest_event(void *opaque, int event)
  638. {
  639. int i;
  640. switch (event) {
  641. case CHR_EVENT_OPENED:
  642. /*
  643. * We used to call qemu_system_reset() here, hoping we could
  644. * use the same process for multiple tests that way. Never
  645. * used. Injects an extra reset even when it's not used, and
  646. * that can mess up tests, e.g. -boot once.
  647. */
  648. for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
  649. irq_levels[i] = 0;
  650. }
  651. qemu_gettimeofday(&start_time);
  652. qtest_opened = true;
  653. if (qtest_log_fp) {
  654. fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
  655. (long) start_time.tv_sec, (long) start_time.tv_usec);
  656. }
  657. break;
  658. case CHR_EVENT_CLOSED:
  659. qtest_opened = false;
  660. if (qtest_log_fp) {
  661. qemu_timeval tv;
  662. qtest_get_time(&tv);
  663. fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
  664. (long) tv.tv_sec, (long) tv.tv_usec);
  665. }
  666. break;
  667. default:
  668. break;
  669. }
  670. }
  671. void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
  672. {
  673. Chardev *chr;
  674. chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
  675. if (chr == NULL) {
  676. error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
  677. qtest_chrdev);
  678. return;
  679. }
  680. if (qtest_log) {
  681. if (strcmp(qtest_log, "none") != 0) {
  682. qtest_log_fp = fopen(qtest_log, "w+");
  683. }
  684. } else {
  685. qtest_log_fp = stderr;
  686. }
  687. qemu_chr_fe_init(&qtest_chr, chr, errp);
  688. qemu_chr_fe_set_handlers(&qtest_chr, qtest_can_read, qtest_read,
  689. qtest_event, NULL, &qtest_chr, NULL, true);
  690. qemu_chr_fe_set_echo(&qtest_chr, true);
  691. inbuf = g_string_new("");
  692. }
  693. bool qtest_driver(void)
  694. {
  695. return qtest_chr.chr != NULL;
  696. }