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285 lines
8.3 KiB
285 lines
8.3 KiB
5 years ago
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#!/usr/bin/env python3
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import sys
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import json
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import argparse
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parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
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parser.add_argument("csr_json", help="CSR JSON file")
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args = parser.parse_args()
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d = json.load(open(args.csr_json))
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kB = 1024
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mB = kB*1024
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aliases = {}
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# Header -------------------------------------------------------------------------------------------
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dts = """
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/dts-v1/;
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "enjoy-digital,litex-vexriscv-soclinux";
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model = "VexRiscv SoCLinux";
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"""
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# Boot Arguments -----------------------------------------------------------------------------------
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# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
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# david shah:
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# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
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#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
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dts += """
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chosen {{
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bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
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linux,initrd-start = <0x{linux_initrd_start:x}>;
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linux,initrd-end = <0x{linux_initrd_end:x}>;
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}};
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""".format(
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main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"],
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main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
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linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
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linux_initrd_end=d["memories"]["main_ram"]["base"] + 42*mB)
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# CPU ----------------------------------------------------------------------------------------------
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dts += """
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cpus {{
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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timebase-frequency = <{sys_clk_freq}>;
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cpu@0 {{
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clock-frequency = <0x0>;
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compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv32";
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reg = <0x0>;
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riscv,isa = "rv32ima";
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sifive,itim = <0x1>;
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status = "okay";
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tlb-split;
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}};
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}};
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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# Memory -------------------------------------------------------------------------------------------
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dts += """
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memory@{main_ram_base:x} {{
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device_type = "memory";
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reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"])
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# SoC ----------------------------------------------------------------------------------------------
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dts += """
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soc {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "simple-bus";
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ranges;
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"""
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# UART -----------------------------------------------------------------------------------------
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if "uart" in d["csr_bases"]:
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aliases["serial0"] = "liteuart0"
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dts += """
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liteuart0: serial@{uart_csr_base:x} {{
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device_type = "serial";
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compatible = "litex,liteuart";
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reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
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status = "okay";
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}};
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""".format(uart_csr_base=d["csr_bases"]["uart"])
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# Ethernet MAC ---------------------------------------------------------------------------------
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if "ethmac" in d["csr_bases"]:
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dts += """
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mac0: mac@{ethmac_csr_base:x} {{
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compatible = "litex,liteeth";
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reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
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0x0 0x{ethphy_csr_base:x} 0x0 0x0a
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0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
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tx-fifo-depth = <{ethmac_tx_slots}>;
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rx-fifo-depth = <{ethmac_rx_slots}>;
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}};
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""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
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ethmac_csr_base=d["csr_bases"]["ethmac"],
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ethmac_mem_base=d["memories"]["ethmac"]["base"],
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ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
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ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
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# Leds -----------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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leds: gpio@{leds_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
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litex,direction = "out";
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status = "disabled";
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}};
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""".format(leds_csr_base=d["csr_bases"]["leds"])
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# RGB Led --------------------------------------------------------------------------------------
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
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clock = <100000000>;
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#pwm-cells = <3>;
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status = "okay";
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}};
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""".format(pwm_name=name,
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pwm_csr_base=d["csr_bases"][name])
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# Switches -------------------------------------------------------------------------------------
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if "switches" in d["csr_bases"]:
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dts += """
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switches: gpio@{switches_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
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litex,direction = "in";
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status = "disabled";
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}};
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""".format(switches_csr_base=d["csr_bases"]["switches"])
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# SPI ------------------------------------------------------------------------------------------
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if "spi" in d["csr_bases"]:
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aliases["spi0"] = "litespi0"
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dts += """
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litespi0: spi@{spi_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1000000>;
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litespi,num-cs = <1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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spidev0: spidev@0 {{
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compatible = "linux,spidev";
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reg = <0 0>;
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spi-max-frequency = <1000000>;
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status = "okay";
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}};
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}};
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""".format(spi_csr_base=d["csr_bases"]["spi"])
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# I2C ------------------------------------------------------------------------------------------
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if "i2c0" in d["csr_bases"]:
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dts += """
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i2c0: i2c@{i2c0_csr_base:x} {{
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compatible = "litex,i2c";
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reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
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status = "okay";
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}};
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""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
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# XADC -----------------------------------------------------------------------------------------
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if "xadc" in d["csr_bases"]:
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dts += """
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hwmon0: xadc@{xadc_csr_base:x} {{
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compatible = "litex,hwmon-xadc";
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reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
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status = "okay";
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}};
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""".format(xadc_csr_base=d["csr_bases"]["xadc"])
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# Framebuffer ----------------------------------------------------------------------------------
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if "framebuffer" in d["csr_bases"]:
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# FIXME: dynamic framebuffer base and size
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framebuffer_base = 0xc8000000
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framebuffer_width = 1280
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framebuffer_height = 720
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dts += """
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framebuffer0: framebuffer@f0000000 {{
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compatible = "simple-framebuffer";
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reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
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width = <{framebuffer_width}>;
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height = <{framebuffer_height}>;
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stride = <{framebuffer_stride}>;
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format = "a8b8g8r8";
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}};
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""".format(framebuffer_base=framebuffer_base,
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framebuffer_width=framebuffer_width,
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framebuffer_height=framebuffer_height,
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framebuffer_size=framebuffer_width*framebuffer_height*4,
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framebuffer_stride=framebuffer_width*4)
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dts += """
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};
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"""
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# Aliases -----------------------------------------------------------------------------------------
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if aliases:
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dts += """
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aliases {
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"""
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for alias in aliases:
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dts += """
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{} = &{};
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""".format(alias, aliases[alias])
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dts += """
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};
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"""
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dts += """
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};
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"""
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# --------------------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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&leds {
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litex,ngpio = <4>;
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status = "okay";
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};
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"""
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if "switches" in d["csr_bases"]:
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dts += """
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&switches {
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litex,ngpio = <4>;
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status = "okay";
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};
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"""
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print(dts)
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