Jeff Moe
5 years ago
parent
212eea8001
commit
c665ff1a66
@ -0,0 +1,16 @@
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# TrellisBoard OpenOCD config
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interface ftdi
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# ftdi_device_desc "TrellisBoard"
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ftdi_vid_pid 0x0403 0x6010
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# channel 1 does not have any functionality
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ftdi_channel 0
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# just TCK TDI TDO TMS, no reset
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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# default speed
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adapter_khz 5000
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# ECP5 device - LFE5UM5G-85F
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
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@ -0,0 +1,36 @@
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--- make.py.orig 2019-10-02 19:59:51.962297746 -0600
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+++ make.py 2019-10-02 20:02:50.549344701 -0600
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@@ -149,6 +149,16 @@
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def load(self):
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os.system("ujprog build/ulx3s/gateware/top.svf")
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+# TrellisBoard support ------------------------------------------------------------------------------------
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+
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+class Trellis(Board):
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+ def __init__(self):
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+ from litex_boards.targets import trellisboard
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+ Board.__init__(self, trellisboard.EthernetSoC, "serial+ethernet")
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+
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+ def load(self):
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+ os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
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+
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# De0Nano support ------------------------------------------------------------------------------------
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class De0Nano(Board):
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@@ -175,6 +185,7 @@
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# Lattice
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"versa_ecp5": VersaECP5,
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"ulx3s": ULX3S,
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+ "trellisboard": Trellis,
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# Altera/Intel
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"de0nano": De0Nano,
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}
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@@ -202,7 +213,7 @@
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for board_name in board_names:
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board = supported_boards[board_name]()
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soc_kwargs = {}
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- if board_name in ["versa_ecp5", "ulx3s"]:
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+ if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
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soc_kwargs["toolchain"] = "trellis"
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soc_kwargs["cpu_variant"] = "linux+no-dsp"
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if board_name in ["de0nano"]:
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@ -0,0 +1,36 @@
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--- make.py.orig 2019-09-21 11:48:48.213955331 -0600
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+++ make.py 2019-09-21 11:50:35.465382876 -0600
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@@ -149,6 +149,16 @@
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def load(self):
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os.system("ujprog build/ulx3s/gateware/top.svf")
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+# TrellisBoard support ------------------------------------------------------------------------------------
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+
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+class Trellis(Board):
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+ def __init__(self):
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+ from litex_boards.targets import trellisboard
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+ Board.__init__(self, trellisboard.EthernetSoC, {"serial", "ethernet"})
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+
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+ def load(self):
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+ os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
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+
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# De0Nano support ------------------------------------------------------------------------------------
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class De0Nano(Board):
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@@ -175,6 +185,7 @@
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# Lattice
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"versa_ecp5": VersaECP5,
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"ulx3s": ULX3S,
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+ "trellisboard": Trellis,
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# Altera/Intel
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"de0nano": De0Nano,
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}
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@@ -202,7 +213,7 @@
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for board_name in board_names:
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board = supported_boards[board_name]()
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soc_kwargs = {}
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- if board_name in ["versa_ecp5", "ulx3s"]:
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+ if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
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soc_kwargs["toolchain"] = "trellis"
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soc_kwargs["cpu_variant"] = "linux+no-dsp"
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soc = SoCLinux(board.soc_cls, **soc_kwargs)
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@ -0,0 +1,35 @@
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--- make.py.orig 2019-09-30 19:28:08.962681010 -0600
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+++ make.py 2019-09-30 19:31:38.401563193 -0600
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@@ -149,6 +149,15 @@
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def load(self):
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os.system("ujprog build/ulx3s/gateware/top.svf")
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+# TrellisBoard support ------------------------------------------------------------------------------------
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+
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+class Trellis(Board):
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+ def __init__(self):
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+ from litex_boards.targets import trellisboard
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+ Board.__init__(self, trellisboard.EthernetSoC, {"serial", "ethernet"})
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+
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+ os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
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+
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# De0Nano support ------------------------------------------------------------------------------------
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class De0Nano(Board):
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@@ -175,6 +184,7 @@
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# Lattice
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"versa_ecp5": VersaECP5,
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"ulx3s": ULX3S,
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+ "trellisboard": Trellis,
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# Altera/Intel
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"de0nano": De0Nano,
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}
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@@ -202,7 +212,7 @@
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for board_name in board_names:
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board = supported_boards[board_name]()
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soc_kwargs = {}
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- if board_name in ["versa_ecp5", "ulx3s"]:
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+ if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
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soc_kwargs["toolchain"] = "trellis"
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soc_kwargs["cpu_variant"] = "linux+no-dsp"
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if board_name in ["de0nano"]:
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@ -0,0 +1,284 @@
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#!/usr/bin/env python3
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import sys
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import json
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import argparse
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parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
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parser.add_argument("csr_json", help="CSR JSON file")
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args = parser.parse_args()
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d = json.load(open(args.csr_json))
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kB = 1024
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mB = kB*1024
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aliases = {}
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# Header -------------------------------------------------------------------------------------------
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dts = """
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/dts-v1/;
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "enjoy-digital,litex-vexriscv-soclinux";
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model = "VexRiscv SoCLinux";
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"""
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# Boot Arguments -----------------------------------------------------------------------------------
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# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
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# david shah:
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# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
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#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
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dts += """
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chosen {{
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bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
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linux,initrd-start = <0x{linux_initrd_start:x}>;
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linux,initrd-end = <0x{linux_initrd_end:x}>;
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}};
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""".format(
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main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"],
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main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
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linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
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linux_initrd_end=d["memories"]["main_ram"]["base"] + 136*mB)
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# CPU ----------------------------------------------------------------------------------------------
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dts += """
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cpus {{
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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timebase-frequency = <{sys_clk_freq}>;
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cpu@0 {{
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clock-frequency = <0x0>;
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compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv32";
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reg = <0x0>;
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riscv,isa = "rv32ima";
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sifive,itim = <0x1>;
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status = "okay";
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tlb-split;
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}};
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}};
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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# Memory -------------------------------------------------------------------------------------------
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dts += """
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memory@{main_ram_base:x} {{
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device_type = "memory";
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reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"])
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# SoC ----------------------------------------------------------------------------------------------
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dts += """
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soc {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "simple-bus";
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ranges;
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"""
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# UART -----------------------------------------------------------------------------------------
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if "uart" in d["csr_bases"]:
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aliases["serial0"] = "liteuart0"
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dts += """
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liteuart0: serial@{uart_csr_base:x} {{
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device_type = "serial";
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compatible = "litex,liteuart";
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reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
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status = "okay";
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}};
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""".format(uart_csr_base=d["csr_bases"]["uart"])
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# Ethernet MAC ---------------------------------------------------------------------------------
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if "ethmac" in d["csr_bases"]:
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dts += """
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mac0: mac@{ethmac_csr_base:x} {{
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compatible = "litex,liteeth";
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reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
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0x0 0x{ethphy_csr_base:x} 0x0 0x0a
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0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
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tx-fifo-depth = <{ethmac_tx_slots}>;
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rx-fifo-depth = <{ethmac_rx_slots}>;
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}};
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""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
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ethmac_csr_base=d["csr_bases"]["ethmac"],
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ethmac_mem_base=d["memories"]["ethmac"]["base"],
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ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
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ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
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# Leds -----------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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leds: gpio@{leds_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
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litex,direction = "out";
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status = "disabled";
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}};
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""".format(leds_csr_base=d["csr_bases"]["leds"])
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# RGB Led --------------------------------------------------------------------------------------
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
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clock = <100000000>;
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#pwm-cells = <3>;
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status = "okay";
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}};
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""".format(pwm_name=name,
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pwm_csr_base=d["csr_bases"][name])
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# Switches -------------------------------------------------------------------------------------
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if "switches" in d["csr_bases"]:
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dts += """
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switches: gpio@{switches_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
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litex,direction = "in";
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status = "disabled";
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}};
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""".format(switches_csr_base=d["csr_bases"]["switches"])
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# SPI ------------------------------------------------------------------------------------------
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if "spi" in d["csr_bases"]:
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aliases["spi0"] = "litespi0"
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dts += """
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litespi0: spi@{spi_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1000000>;
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litespi,num-cs = <1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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spidev0: spidev@0 {{
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compatible = "linux,spidev";
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reg = <0 0>;
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spi-max-frequency = <1000000>;
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status = "okay";
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}};
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}};
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""".format(spi_csr_base=d["csr_bases"]["spi"])
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# I2C ------------------------------------------------------------------------------------------
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if "i2c0" in d["csr_bases"]:
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dts += """
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i2c0: i2c@{i2c0_csr_base:x} {{
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compatible = "litex,i2c";
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reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
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status = "okay";
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}};
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""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
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# XADC -----------------------------------------------------------------------------------------
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if "xadc" in d["csr_bases"]:
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dts += """
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hwmon0: xadc@{xadc_csr_base:x} {{
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compatible = "litex,hwmon-xadc";
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reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
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status = "okay";
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}};
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""".format(xadc_csr_base=d["csr_bases"]["xadc"])
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# Framebuffer ----------------------------------------------------------------------------------
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if "framebuffer" in d["csr_bases"]:
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# FIXME: dynamic framebuffer base and size
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framebuffer_base = 0xc8000000
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framebuffer_width = 1280
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framebuffer_height = 720
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dts += """
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framebuffer0: framebuffer@f0000000 {{
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compatible = "simple-framebuffer";
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reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
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width = <{framebuffer_width}>;
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height = <{framebuffer_height}>;
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stride = <{framebuffer_stride}>;
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format = "a8b8g8r8";
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}};
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""".format(framebuffer_base=framebuffer_base,
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framebuffer_width=framebuffer_width,
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framebuffer_height=framebuffer_height,
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framebuffer_size=framebuffer_width*framebuffer_height*4,
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framebuffer_stride=framebuffer_width*4)
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dts += """
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};
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"""
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# Aliases -----------------------------------------------------------------------------------------
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if aliases:
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dts += """
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aliases {
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"""
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for alias in aliases:
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dts += """
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{} = &{};
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""".format(alias, aliases[alias])
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dts += """
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};
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"""
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dts += """
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};
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"""
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# --------------------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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&leds {
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litex,ngpio = <4>;
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status = "okay";
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};
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"""
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if "switches" in d["csr_bases"]:
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dts += """
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&switches {
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litex,ngpio = <4>;
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status = "okay";
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};
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"""
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print(dts)
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@ -0,0 +1,284 @@
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#!/usr/bin/env python3
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import sys
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import json
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import argparse
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parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
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parser.add_argument("csr_json", help="CSR JSON file")
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args = parser.parse_args()
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d = json.load(open(args.csr_json))
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kB = 1024
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mB = kB*1024
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aliases = {}
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# Header -------------------------------------------------------------------------------------------
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dts = """
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/dts-v1/;
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/ {
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#address-cells = <0x2>;
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||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 136*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 24*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 32*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 40*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 42*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 44*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 46*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 48*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 50*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 54*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi rootwait root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 72*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,280 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} console=liteuart earlycon=sbi ip=dhcp root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=eth0:dhcp root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,280 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,284 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import json
|
||||
import argparse
|
||||
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
args = parser.parse_args()
|
||||
|
||||
d = json.load(open(args.csr_json))
|
||||
|
||||
kB = 1024
|
||||
mB = kB*1024
|
||||
|
||||
aliases = {}
|
||||
|
||||
# Header -------------------------------------------------------------------------------------------
|
||||
|
||||
dts = """
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "enjoy-digital,litex-vexriscv-soclinux";
|
||||
model = "VexRiscv SoCLinux";
|
||||
"""
|
||||
|
||||
# Boot Arguments -----------------------------------------------------------------------------------
|
||||
|
||||
# bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992 debug init=/sbin/init swiotlb=32";
|
||||
# david shah:
|
||||
# bootargs = "mem=1024M@0x40000000 rootwait console=hvc0 root=/dev/nfs nfsroot=192.168.7.1:/srv/nfsroot,rsize=1024,wsize=1024,nolock,udp,nfsvers=3 ip=192.168.7.100:192.168.7.1:192.168.7.1:255.255.255.0:vexriscv:eth0:none:8.8.8.8 init=/sbin/init swiotlb=32";
|
||||
#bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi ip=192.168.110.26::192.168.110.252:255.255.255.0:trellisboard:eth0 root=nbd:192.168.110.63:8992:ext4 debug init=/sbin/init swiotlb=32";
|
||||
|
||||
dts += """
|
||||
chosen {{
|
||||
bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi root=/dev/ram0 debug init=/sbin/init swiotlb=32";
|
||||
linux,initrd-start = <0x{linux_initrd_start:x}>;
|
||||
linux,initrd-end = <0x{linux_initrd_end:x}>;
|
||||
}};
|
||||
""".format(
|
||||
main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"],
|
||||
main_ram_size_mb=d["memories"]["main_ram"]["size"]//mB,
|
||||
|
||||
linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
|
||||
linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
|
||||
|
||||
# CPU ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
cpus {{
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
timebase-frequency = <{sys_clk_freq}>;
|
||||
|
||||
cpu@0 {{
|
||||
clock-frequency = <0x0>;
|
||||
compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x40>;
|
||||
d-cache-sets = <0x40>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-tlb-sets = <0x1>;
|
||||
d-tlb-size = <0x20>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x40>;
|
||||
i-cache-sets = <0x40>;
|
||||
i-cache-size = <0x8000>;
|
||||
i-tlb-sets = <0x1>;
|
||||
i-tlb-size = <0x20>;
|
||||
mmu-type = "riscv,sv32";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv32ima";
|
||||
sifive,itim = <0x1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
}};
|
||||
}};
|
||||
""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
|
||||
|
||||
# Memory -------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
memory@{main_ram_base:x} {{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x{main_ram_base:x} 0x1 0x{main_ram_size:x}>;
|
||||
}};
|
||||
""".format(main_ram_base=d["memories"]["main_ram"]["base"],
|
||||
main_ram_size=d["memories"]["main_ram"]["size"])
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
dts += """
|
||||
soc {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
"""
|
||||
|
||||
# UART -----------------------------------------------------------------------------------------
|
||||
|
||||
if "uart" in d["csr_bases"]:
|
||||
aliases["serial0"] = "liteuart0"
|
||||
dts += """
|
||||
liteuart0: serial@{uart_csr_base:x} {{
|
||||
device_type = "serial";
|
||||
compatible = "litex,liteuart";
|
||||
reg = <0x0 0x{uart_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(uart_csr_base=d["csr_bases"]["uart"])
|
||||
|
||||
# Ethernet MAC ---------------------------------------------------------------------------------
|
||||
|
||||
if "ethmac" in d["csr_bases"]:
|
||||
dts += """
|
||||
mac0: mac@{ethmac_csr_base:x} {{
|
||||
compatible = "litex,liteeth";
|
||||
reg = <0x0 0x{ethmac_csr_base:x} 0x0 0x7c
|
||||
0x0 0x{ethphy_csr_base:x} 0x0 0x0a
|
||||
0x0 0x{ethmac_mem_base:x} 0x0 0x2000>;
|
||||
tx-fifo-depth = <{ethmac_tx_slots}>;
|
||||
rx-fifo-depth = <{ethmac_rx_slots}>;
|
||||
}};
|
||||
""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
|
||||
ethmac_csr_base=d["csr_bases"]["ethmac"],
|
||||
ethmac_mem_base=d["memories"]["ethmac"]["base"],
|
||||
ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
|
||||
ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
|
||||
|
||||
# Leds -----------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
leds: gpio@{leds_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{leds_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "out";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(leds_csr_base=d["csr_bases"]["leds"])
|
||||
|
||||
# RGB Led --------------------------------------------------------------------------------------
|
||||
|
||||
for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
|
||||
if name in d["csr_bases"]:
|
||||
dts += """
|
||||
{pwm_name}: pwm@{pwm_csr_base:x} {{
|
||||
compatible = "litex,pwm";
|
||||
reg = <0x0 0x{pwm_csr_base:x} 0x0 0x24>;
|
||||
clock = <100000000>;
|
||||
#pwm-cells = <3>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(pwm_name=name,
|
||||
pwm_csr_base=d["csr_bases"][name])
|
||||
|
||||
# Switches -------------------------------------------------------------------------------------
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
switches: gpio@{switches_csr_base:x} {{
|
||||
compatible = "litex,gpio";
|
||||
reg = <0x0 0x{switches_csr_base:x} 0x0 0x4>;
|
||||
litex,direction = "in";
|
||||
status = "disabled";
|
||||
}};
|
||||
""".format(switches_csr_base=d["csr_bases"]["switches"])
|
||||
|
||||
# SPI ------------------------------------------------------------------------------------------
|
||||
|
||||
if "spi" in d["csr_bases"]:
|
||||
aliases["spi0"] = "litespi0"
|
||||
|
||||
dts += """
|
||||
litespi0: spi@{spi_csr_base:x} {{
|
||||
compatible = "litex,litespi";
|
||||
reg = <0x0 0x{spi_csr_base:x} 0x0 0x100>;
|
||||
status = "okay";
|
||||
|
||||
litespi,max-bpw = <8>;
|
||||
litespi,sck-frequency = <1000000>;
|
||||
litespi,num-cs = <1>;
|
||||
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
spidev0: spidev@0 {{
|
||||
compatible = "linux,spidev";
|
||||
reg = <0 0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
status = "okay";
|
||||
}};
|
||||
}};
|
||||
""".format(spi_csr_base=d["csr_bases"]["spi"])
|
||||
|
||||
# I2C ------------------------------------------------------------------------------------------
|
||||
|
||||
if "i2c0" in d["csr_bases"]:
|
||||
dts += """
|
||||
i2c0: i2c@{i2c0_csr_base:x} {{
|
||||
compatible = "litex,i2c";
|
||||
reg = <0x0 0x{i2c0_csr_base:x} 0x0 0x5>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
|
||||
|
||||
# XADC -----------------------------------------------------------------------------------------
|
||||
|
||||
if "xadc" in d["csr_bases"]:
|
||||
dts += """
|
||||
hwmon0: xadc@{xadc_csr_base:x} {{
|
||||
compatible = "litex,hwmon-xadc";
|
||||
reg = <0x0 0x{xadc_csr_base:x} 0x0 0x20>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(xadc_csr_base=d["csr_bases"]["xadc"])
|
||||
|
||||
# Framebuffer ----------------------------------------------------------------------------------
|
||||
|
||||
if "framebuffer" in d["csr_bases"]:
|
||||
# FIXME: dynamic framebuffer base and size
|
||||
framebuffer_base = 0xc8000000
|
||||
framebuffer_width = 1280
|
||||
framebuffer_height = 720
|
||||
dts += """
|
||||
framebuffer0: framebuffer@f0000000 {{
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0x0 0x{framebuffer_base:x} 0x0 0x{framebuffer_size:x}>;
|
||||
width = <{framebuffer_width}>;
|
||||
height = <{framebuffer_height}>;
|
||||
stride = <{framebuffer_stride}>;
|
||||
format = "a8b8g8r8";
|
||||
}};
|
||||
""".format(framebuffer_base=framebuffer_base,
|
||||
framebuffer_width=framebuffer_width,
|
||||
framebuffer_height=framebuffer_height,
|
||||
framebuffer_size=framebuffer_width*framebuffer_height*4,
|
||||
framebuffer_stride=framebuffer_width*4)
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases -----------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
aliases {
|
||||
"""
|
||||
for alias in aliases:
|
||||
dts += """
|
||||
{} = &{};
|
||||
""".format(alias, aliases[alias])
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# --------------------------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
&leds {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
if "switches" in d["csr_bases"]:
|
||||
dts += """
|
||||
&switches {
|
||||
litex,ngpio = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
"""
|
||||
|
||||
print(dts)
|
||||
@ -0,0 +1,1922 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/riscv 5.0.13 Kernel Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# Compiler: riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2019.11-git-00614-g5a9348d370) 8.3.0
|
||||
#
|
||||
CONFIG_CC_IS_GCC=y
|
||||
CONFIG_GCC_VERSION=80300
|
||||
CONFIG_CLANG_VERSION=0
|
||||
CONFIG_CC_HAS_ASM_GOTO=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
# CONFIG_COMPILE_TEST is not set
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_BUILD_SALT=""
|
||||
CONFIG_DEFAULT_HOSTNAME="(none)"
|
||||
CONFIG_SWAP=y
|
||||
# CONFIG_SYSVIPC is not set
|
||||
# CONFIG_POSIX_MQUEUE is not set
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
# CONFIG_USELIB is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
||||
|
||||
#
|
||||
# IRQ subsystem
|
||||
#
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
|
||||
#
|
||||
# Timers subsystem
|
||||
#
|
||||
CONFIG_HZ_PERIODIC=y
|
||||
# CONFIG_NO_HZ_IDLE is not set
|
||||
# CONFIG_NO_HZ is not set
|
||||
# CONFIG_HIGH_RES_TIMERS is not set
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
|
||||
#
|
||||
# CPU/Task time and stats accounting
|
||||
#
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_PSI is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_TINY_RCU=y
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_TINY_SRCU=y
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=17
|
||||
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
# CONFIG_CGROUPS is not set
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_UTS_NS=y
|
||||
# CONFIG_USER_NS is not set
|
||||
CONFIG_PID_NS=y
|
||||
CONFIG_NET_NS=y
|
||||
# CONFIG_CHECKPOINT_RESTORE is not set
|
||||
# CONFIG_SCHED_AUTOGROUP is not set
|
||||
# CONFIG_SYSFS_DEPRECATED is not set
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_ANON_INODES=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_BPF=y
|
||||
# CONFIG_EXPERT is not set
|
||||
CONFIG_MULTIUSER=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_POSIX_TIMERS=y
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_FUTEX_PI=y
|
||||
CONFIG_HAVE_FUTEX_CMPXCHG=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SIGNALFD=y
|
||||
CONFIG_TIMERFD=y
|
||||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_ADVISE_SYSCALLS=y
|
||||
CONFIG_MEMBARRIER=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_BASE_RELATIVE=y
|
||||
# CONFIG_BPF_SYSCALL is not set
|
||||
# CONFIG_USERFAULTFD is not set
|
||||
# CONFIG_EMBEDDED is not set
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
|
||||
#
|
||||
# Kernel Performance Events And Counters
|
||||
#
|
||||
# CONFIG_PERF_EVENTS is not set
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_COMPAT_BRK=y
|
||||
# CONFIG_SLAB is not set
|
||||
CONFIG_SLUB=y
|
||||
CONFIG_SLAB_MERGE_DEFAULT=y
|
||||
# CONFIG_SLAB_FREELIST_RANDOM is not set
|
||||
# CONFIG_SLAB_FREELIST_HARDENED is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
CONFIG_32BIT=y
|
||||
CONFIG_RISCV=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
CONFIG_STACKTRACE_SUPPORT=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
|
||||
#
|
||||
# Platform type
|
||||
#
|
||||
CONFIG_ARCH_RV32I=y
|
||||
# CONFIG_ARCH_RV64I is not set
|
||||
CONFIG_CMODEL_MEDLOW=y
|
||||
# CONFIG_CMODEL_MEDANY is not set
|
||||
CONFIG_MAXPHYSMEM_2GB=y
|
||||
# CONFIG_SMP is not set
|
||||
CONFIG_TUNE_GENERIC=y
|
||||
# CONFIG_RISCV_ISA_C is not set
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
# CONFIG_FPU is not set
|
||||
|
||||
#
|
||||
# Kernel features
|
||||
#
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
|
||||
#
|
||||
# Boot options
|
||||
#
|
||||
CONFIG_CMDLINE=""
|
||||
|
||||
#
|
||||
# Power management options
|
||||
#
|
||||
# CONFIG_PM is not set
|
||||
|
||||
#
|
||||
# General architecture-dependent options
|
||||
#
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_CC_HAS_STACKPROTECTOR_NONE=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
# CONFIG_REFCOUNT_FULL is not set
|
||||
|
||||
#
|
||||
# GCOV-based kernel profiling
|
||||
#
|
||||
CONFIG_PLUGIN_HOSTCC="g++"
|
||||
CONFIG_RT_MUTEXES=y
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_MODULES is not set
|
||||
CONFIG_BLOCK=y
|
||||
CONFIG_LBDAF=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
# CONFIG_BLK_DEV_BSGLIB is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
# CONFIG_BLK_DEV_ZONED is not set
|
||||
# CONFIG_BLK_CMDLINE_PARSER is not set
|
||||
# CONFIG_BLK_WBT is not set
|
||||
# CONFIG_BLK_SED_OPAL is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
CONFIG_MQ_IOSCHED_KYBER=y
|
||||
# CONFIG_IOSCHED_BFQ is not set
|
||||
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
|
||||
CONFIG_INLINE_READ_UNLOCK=y
|
||||
CONFIG_INLINE_READ_UNLOCK_IRQ=y
|
||||
CONFIG_INLINE_WRITE_UNLOCK=y
|
||||
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
#
|
||||
CONFIG_BINFMT_ELF=y
|
||||
CONFIG_ELFCORE=y
|
||||
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
|
||||
CONFIG_BINFMT_SCRIPT=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_COREDUMP=y
|
||||
|
||||
#
|
||||
# Memory Management options
|
||||
#
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_COMPACTION=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
# CONFIG_KSM is not set
|
||||
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
|
||||
CONFIG_NEED_PER_CPU_KM=y
|
||||
# CONFIG_CLEANCACHE is not set
|
||||
# CONFIG_FRONTSWAP is not set
|
||||
# CONFIG_CMA is not set
|
||||
# CONFIG_ZPOOL is not set
|
||||
# CONFIG_ZBUD is not set
|
||||
# CONFIG_ZSMALLOC is not set
|
||||
# CONFIG_IDLE_PAGE_TRACKING is not set
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_BENCHMARK is not set
|
||||
CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_SKB_EXTENSIONS=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_PACKET is not set
|
||||
# CONFIG_UNIX is not set
|
||||
# CONFIG_TLS is not set
|
||||
CONFIG_XFRM=y
|
||||
# CONFIG_XFRM_USER is not set
|
||||
# CONFIG_XFRM_INTERFACE is not set
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
# CONFIG_XFRM_MIGRATE is not set
|
||||
# CONFIG_XFRM_STATISTICS is not set
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IP_MULTICAST is not set
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
# CONFIG_IP_PNP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE_DEMUX is not set
|
||||
CONFIG_NET_IP_TUNNEL=y
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_NET_IPVTI is not set
|
||||
# CONFIG_NET_FOU is not set
|
||||
# CONFIG_NET_FOU_IP_TUNNELS is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
CONFIG_INET_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_INET_UDP_DIAG is not set
|
||||
# CONFIG_INET_RAW_DIAG is not set
|
||||
# CONFIG_INET_DIAG_DESTROY is not set
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
# CONFIG_TCP_MD5SIG is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_IPV6_ROUTER_PREF is not set
|
||||
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
|
||||
# CONFIG_INET6_AH is not set
|
||||
# CONFIG_INET6_ESP is not set
|
||||
# CONFIG_INET6_IPCOMP is not set
|
||||
# CONFIG_IPV6_MIP6 is not set
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET6_XFRM_MODE_BEET=y
|
||||
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
|
||||
# CONFIG_IPV6_VTI is not set
|
||||
CONFIG_IPV6_SIT=y
|
||||
# CONFIG_IPV6_SIT_6RD is not set
|
||||
CONFIG_IPV6_NDISC_NODETYPE=y
|
||||
# CONFIG_IPV6_TUNNEL is not set
|
||||
# CONFIG_IPV6_MULTIPLE_TABLES is not set
|
||||
# CONFIG_IPV6_MROUTE is not set
|
||||
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
|
||||
# CONFIG_IPV6_SEG6_HMAC is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
# CONFIG_BPFILTER is not set
|
||||
# CONFIG_IP_DCCP is not set
|
||||
# CONFIG_IP_SCTP is not set
|
||||
# CONFIG_RDS is not set
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_L2TP is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
# CONFIG_NET_DSA is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_6LOWPAN is not set
|
||||
# CONFIG_IEEE802154 is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
# CONFIG_BATMAN_ADV is not set
|
||||
# CONFIG_OPENVSWITCH is not set
|
||||
# CONFIG_VSOCKETS is not set
|
||||
# CONFIG_NETLINK_DIAG is not set
|
||||
# CONFIG_MPLS is not set
|
||||
# CONFIG_NET_NSH is not set
|
||||
# CONFIG_HSR is not set
|
||||
# CONFIG_NET_SWITCHDEV is not set
|
||||
# CONFIG_NET_L3_MASTER_DEV is not set
|
||||
# CONFIG_NET_NCSI is not set
|
||||
CONFIG_NET_RX_BUSY_POLL=y
|
||||
CONFIG_BQL=y
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_CAN is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
# CONFIG_AF_KCM is not set
|
||||
CONFIG_WIRELESS=y
|
||||
# CONFIG_CFG80211 is not set
|
||||
|
||||
#
|
||||
# CFG80211 needs to be enabled for MAC80211
|
||||
#
|
||||
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
|
||||
# CONFIG_WIMAX is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
# CONFIG_NET_9P is not set
|
||||
# CONFIG_CAIF is not set
|
||||
# CONFIG_CEPH_LIB is not set
|
||||
# CONFIG_NFC is not set
|
||||
# CONFIG_PSAMPLE is not set
|
||||
# CONFIG_NET_IFE is not set
|
||||
# CONFIG_LWTUNNEL is not set
|
||||
CONFIG_DST_CACHE=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
# CONFIG_NET_DEVLINK is not set
|
||||
CONFIG_MAY_USE_DEVLINK=y
|
||||
# CONFIG_FAILOVER is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
CONFIG_HAVE_PCI=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_UEVENT_HELPER=y
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
|
||||
#
|
||||
# Firmware loader
|
||||
#
|
||||
CONFIG_FW_LOADER=y
|
||||
CONFIG_EXTRA_FIRMWARE=""
|
||||
# CONFIG_FW_LOADER_USER_HELPER is not set
|
||||
CONFIG_ALLOW_DEV_COREDUMP=y
|
||||
CONFIG_GENERIC_CPU_DEVICES=y
|
||||
|
||||
#
|
||||
# Bus devices
|
||||
#
|
||||
# CONFIG_CONNECTOR is not set
|
||||
# CONFIG_GNSS is not set
|
||||
# CONFIG_MTD is not set
|
||||
CONFIG_DTC=y
|
||||
CONFIG_OF=y
|
||||
# CONFIG_OF_UNITTEST is not set
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_MDIO=y
|
||||
# CONFIG_OF_OVERLAY is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_DEV_NULL_BLK is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_DRBD is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_BLK_DEV_RBD is not set
|
||||
|
||||
#
|
||||
# NVME Support
|
||||
#
|
||||
# CONFIG_NVME_FC is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
# CONFIG_AD525X_DPOT is not set
|
||||
# CONFIG_DUMMY_IRQ is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_APDS9802ALS is not set
|
||||
# CONFIG_ISL29003 is not set
|
||||
# CONFIG_ISL29020 is not set
|
||||
# CONFIG_SENSORS_TSL2550 is not set
|
||||
# CONFIG_SENSORS_BH1770 is not set
|
||||
# CONFIG_SENSORS_APDS990X is not set
|
||||
# CONFIG_HMC6352 is not set
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_USB_SWITCH_FSA9480 is not set
|
||||
# CONFIG_LATTICE_ECP3_CONFIG is not set
|
||||
# CONFIG_SRAM is not set
|
||||
# CONFIG_PVPANIC is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
# CONFIG_EEPROM_AT24 is not set
|
||||
# CONFIG_EEPROM_AT25 is not set
|
||||
# CONFIG_EEPROM_LEGACY is not set
|
||||
# CONFIG_EEPROM_MAX6875 is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_EEPROM_93XX46 is not set
|
||||
# CONFIG_EEPROM_IDT_89HPESX is not set
|
||||
# CONFIG_EEPROM_EE1004 is not set
|
||||
|
||||
#
|
||||
# Texas Instruments shared transport line discipline
|
||||
#
|
||||
# CONFIG_TI_ST is not set
|
||||
# CONFIG_SENSORS_LIS3_SPI is not set
|
||||
# CONFIG_SENSORS_LIS3_I2C is not set
|
||||
# CONFIG_ALTERA_STAPL is not set
|
||||
|
||||
#
|
||||
# Intel MIC & related support
|
||||
#
|
||||
|
||||
#
|
||||
# Intel MIC Bus Driver
|
||||
#
|
||||
|
||||
#
|
||||
# SCIF Bus Driver
|
||||
#
|
||||
|
||||
#
|
||||
# VOP Bus Driver
|
||||
#
|
||||
|
||||
#
|
||||
# Intel MIC Host Driver
|
||||
#
|
||||
|
||||
#
|
||||
# Intel MIC Card Driver
|
||||
#
|
||||
|
||||
#
|
||||
# SCIF Driver
|
||||
#
|
||||
|
||||
#
|
||||
# Intel MIC Coprocessor State Management (COSM) Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# VOP Driver
|
||||
#
|
||||
# CONFIG_ECHO is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_SCSI_MOD=y
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_ATA is not set
|
||||
# CONFIG_MD is not set
|
||||
# CONFIG_TARGET_CORE is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_NET_CORE=y
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_NET_TEAM is not set
|
||||
# CONFIG_MACVLAN is not set
|
||||
# CONFIG_VXLAN is not set
|
||||
# CONFIG_GENEVE is not set
|
||||
# CONFIG_GTP is not set
|
||||
# CONFIG_MACSEC is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_TUN is not set
|
||||
# CONFIG_TUN_VNET_CROSS_LE is not set
|
||||
# CONFIG_VETH is not set
|
||||
# CONFIG_NLMON is not set
|
||||
|
||||
#
|
||||
# CAIF transport drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Distributed Switch Architecture drivers
|
||||
#
|
||||
CONFIG_ETHERNET=y
|
||||
CONFIG_NET_VENDOR_ALACRITECH=y
|
||||
# CONFIG_ALTERA_TSE is not set
|
||||
CONFIG_NET_VENDOR_AMAZON=y
|
||||
CONFIG_NET_VENDOR_AQUANTIA=y
|
||||
CONFIG_NET_VENDOR_ARC=y
|
||||
CONFIG_NET_VENDOR_AURORA=y
|
||||
# CONFIG_AURORA_NB8800 is not set
|
||||
CONFIG_NET_VENDOR_BROADCOM=y
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_BCMGENET is not set
|
||||
# CONFIG_SYSTEMPORT is not set
|
||||
CONFIG_NET_VENDOR_CADENCE=y
|
||||
# CONFIG_MACB is not set
|
||||
CONFIG_NET_VENDOR_CAVIUM=y
|
||||
CONFIG_NET_VENDOR_CORTINA=y
|
||||
# CONFIG_GEMINI_ETHERNET is not set
|
||||
# CONFIG_DNET is not set
|
||||
CONFIG_NET_VENDOR_EZCHIP=y
|
||||
# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
|
||||
CONFIG_NET_VENDOR_HUAWEI=y
|
||||
CONFIG_NET_VENDOR_I825XX=y
|
||||
CONFIG_NET_VENDOR_INTEL=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
CONFIG_NET_VENDOR_MARVELL=y
|
||||
# CONFIG_MVMDIO is not set
|
||||
CONFIG_NET_VENDOR_MELLANOX=y
|
||||
# CONFIG_MLXSW_CORE is not set
|
||||
# CONFIG_MLXFW is not set
|
||||
CONFIG_NET_VENDOR_MICREL=y
|
||||
# CONFIG_KS8851 is not set
|
||||
# CONFIG_KS8851_MLL is not set
|
||||
CONFIG_NET_VENDOR_MICROCHIP=y
|
||||
# CONFIG_ENC28J60 is not set
|
||||
# CONFIG_ENCX24J600 is not set
|
||||
CONFIG_NET_VENDOR_MICROSEMI=y
|
||||
CONFIG_NET_VENDOR_NATSEMI=y
|
||||
CONFIG_NET_VENDOR_NETRONOME=y
|
||||
CONFIG_NET_VENDOR_NI=y
|
||||
# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
|
||||
CONFIG_NET_VENDOR_8390=y
|
||||
# CONFIG_ETHOC is not set
|
||||
CONFIG_NET_VENDOR_QUALCOMM=y
|
||||
# CONFIG_QCA7000_SPI is not set
|
||||
# CONFIG_QCOM_EMAC is not set
|
||||
# CONFIG_RMNET is not set
|
||||
CONFIG_NET_VENDOR_RENESAS=y
|
||||
CONFIG_NET_VENDOR_ROCKER=y
|
||||
CONFIG_NET_VENDOR_SAMSUNG=y
|
||||
# CONFIG_SXGBE_ETH is not set
|
||||
CONFIG_NET_VENDOR_SEEQ=y
|
||||
CONFIG_NET_VENDOR_SOLARFLARE=y
|
||||
CONFIG_NET_VENDOR_SOCIONEXT=y
|
||||
CONFIG_NET_VENDOR_STMICRO=y
|
||||
# CONFIG_STMMAC_ETH is not set
|
||||
CONFIG_NET_VENDOR_SYNOPSYS=y
|
||||
# CONFIG_DWC_XLGMAC is not set
|
||||
CONFIG_NET_VENDOR_VIA=y
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_VIA_VELOCITY is not set
|
||||
CONFIG_NET_VENDOR_WIZNET=y
|
||||
# CONFIG_WIZNET_W5100 is not set
|
||||
# CONFIG_WIZNET_W5300 is not set
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
# CONFIG_MDIO_BCM_UNIMAC is not set
|
||||
# CONFIG_MDIO_BITBANG is not set
|
||||
# CONFIG_MDIO_BUS_MUX_GPIO is not set
|
||||
# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
|
||||
# CONFIG_MDIO_HISI_FEMAC is not set
|
||||
# CONFIG_MDIO_MSCC_MIIM is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_SWPHY=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_AMD_PHY is not set
|
||||
# CONFIG_AQUANTIA_PHY is not set
|
||||
# CONFIG_ASIX_PHY is not set
|
||||
# CONFIG_AT803X_PHY is not set
|
||||
# CONFIG_BCM7XXX_PHY is not set
|
||||
# CONFIG_BCM87XX_PHY is not set
|
||||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_CORTINA_PHY is not set
|
||||
# CONFIG_DAVICOM_PHY is not set
|
||||
# CONFIG_DP83822_PHY is not set
|
||||
# CONFIG_DP83TC811_PHY is not set
|
||||
# CONFIG_DP83848_PHY is not set
|
||||
# CONFIG_DP83867_PHY is not set
|
||||
CONFIG_FIXED_PHY=y
|
||||
# CONFIG_ICPLUS_PHY is not set
|
||||
# CONFIG_INTEL_XWAY_PHY is not set
|
||||
# CONFIG_LSI_ET1011C_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_MARVELL_PHY is not set
|
||||
# CONFIG_MARVELL_10G_PHY is not set
|
||||
# CONFIG_MICREL_PHY is not set
|
||||
# CONFIG_MICROCHIP_PHY is not set
|
||||
# CONFIG_MICROCHIP_T1_PHY is not set
|
||||
# CONFIG_MICROSEMI_PHY is not set
|
||||
# CONFIG_NATIONAL_PHY is not set
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
# CONFIG_RENESAS_PHY is not set
|
||||
# CONFIG_ROCKCHIP_PHY is not set
|
||||
# CONFIG_SMSC_PHY is not set
|
||||
# CONFIG_STE10XP is not set
|
||||
# CONFIG_TERANETICS_PHY is not set
|
||||
# CONFIG_VITESSE_PHY is not set
|
||||
# CONFIG_XILINX_GMII2RGMII is not set
|
||||
# CONFIG_MICREL_KS8995MA is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
|
||||
#
|
||||
# Host-side USB support is needed for USB Network Adapter support
|
||||
#
|
||||
CONFIG_WLAN=y
|
||||
CONFIG_WLAN_VENDOR_ADMTEK=y
|
||||
CONFIG_WLAN_VENDOR_ATH=y
|
||||
# CONFIG_ATH_DEBUG is not set
|
||||
CONFIG_WLAN_VENDOR_ATMEL=y
|
||||
CONFIG_WLAN_VENDOR_BROADCOM=y
|
||||
CONFIG_WLAN_VENDOR_CISCO=y
|
||||
CONFIG_WLAN_VENDOR_INTEL=y
|
||||
CONFIG_WLAN_VENDOR_INTERSIL=y
|
||||
# CONFIG_HOSTAP is not set
|
||||
CONFIG_WLAN_VENDOR_MARVELL=y
|
||||
CONFIG_WLAN_VENDOR_MEDIATEK=y
|
||||
CONFIG_WLAN_VENDOR_RALINK=y
|
||||
CONFIG_WLAN_VENDOR_REALTEK=y
|
||||
CONFIG_WLAN_VENDOR_RSI=y
|
||||
CONFIG_WLAN_VENDOR_ST=y
|
||||
CONFIG_WLAN_VENDOR_TI=y
|
||||
CONFIG_WLAN_VENDOR_ZYDAS=y
|
||||
CONFIG_WLAN_VENDOR_QUANTENNA=y
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_NET_FAILOVER is not set
|
||||
# CONFIG_ISDN is not set
|
||||
# CONFIG_NVM is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
# CONFIG_INPUT_MATRIXKMAP is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
# CONFIG_KEYBOARD_ADP5588 is not set
|
||||
# CONFIG_KEYBOARD_ADP5589 is not set
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
# CONFIG_KEYBOARD_QT1070 is not set
|
||||
# CONFIG_KEYBOARD_QT2160 is not set
|
||||
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_GPIO is not set
|
||||
# CONFIG_KEYBOARD_GPIO_POLLED is not set
|
||||
# CONFIG_KEYBOARD_TCA6416 is not set
|
||||
# CONFIG_KEYBOARD_TCA8418 is not set
|
||||
# CONFIG_KEYBOARD_MATRIX is not set
|
||||
# CONFIG_KEYBOARD_LM8333 is not set
|
||||
# CONFIG_KEYBOARD_MAX7359 is not set
|
||||
# CONFIG_KEYBOARD_MCS is not set
|
||||
# CONFIG_KEYBOARD_MPR121 is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
# CONFIG_KEYBOARD_OPENCORES is not set
|
||||
# CONFIG_KEYBOARD_SAMSUNG is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_OMAP4 is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
CONFIG_MOUSE_PS2_ALPS=y
|
||||
CONFIG_MOUSE_PS2_BYD=y
|
||||
CONFIG_MOUSE_PS2_LOGIPS2PP=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
|
||||
CONFIG_MOUSE_PS2_CYPRESS=y
|
||||
CONFIG_MOUSE_PS2_TRACKPOINT=y
|
||||
# CONFIG_MOUSE_PS2_ELANTECH is not set
|
||||
# CONFIG_MOUSE_PS2_SENTELIC is not set
|
||||
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
|
||||
CONFIG_MOUSE_PS2_FOCALTECH=y
|
||||
CONFIG_MOUSE_PS2_SMBUS=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_APPLETOUCH is not set
|
||||
# CONFIG_MOUSE_BCM5974 is not set
|
||||
# CONFIG_MOUSE_CYAPA is not set
|
||||
# CONFIG_MOUSE_ELAN_I2C is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
# CONFIG_MOUSE_GPIO is not set
|
||||
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
|
||||
# CONFIG_MOUSE_SYNAPTICS_USB is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_RMI4_CORE is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_SERIO_ALTERA_PS2 is not set
|
||||
# CONFIG_SERIO_PS2MULT is not set
|
||||
# CONFIG_SERIO_ARC_PS2 is not set
|
||||
# CONFIG_SERIO_APBPS2 is not set
|
||||
# CONFIG_SERIO_OLPC_APSP is not set
|
||||
# CONFIG_SERIO_GPIO_PS2 is not set
|
||||
# CONFIG_USERIO is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
CONFIG_TTY=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
# CONFIG_N_GSM is not set
|
||||
# CONFIG_TRACE_SINK is not set
|
||||
CONFIG_LDISC_AUTOLOAD=y
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVKMEM is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
CONFIG_SERIAL_EARLYCON=y
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
# CONFIG_SERIAL_MAX3100 is not set
|
||||
# CONFIG_SERIAL_MAX310X is not set
|
||||
# CONFIG_SERIAL_UARTLITE is not set
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_SCCNXP is not set
|
||||
# CONFIG_SERIAL_SC16IS7XX is not set
|
||||
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
|
||||
# CONFIG_SERIAL_ALTERA_UART is not set
|
||||
# CONFIG_SERIAL_IFX6X60 is not set
|
||||
# CONFIG_SERIAL_XILINX_PS_UART is not set
|
||||
# CONFIG_SERIAL_ARC is not set
|
||||
# CONFIG_SERIAL_FSL_LPUART is not set
|
||||
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_NR_PORTS=1
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
# CONFIG_SERIAL_DEV_BUS is not set
|
||||
# CONFIG_HVC_RISCV_SBI is not set
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
# CONFIG_TCG_TPM is not set
|
||||
# CONFIG_XILLYBUS is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_MUX is not set
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_ALGOBIT=y
|
||||
|
||||
#
|
||||
# I2C Hardware Bus support
|
||||
#
|
||||
|
||||
#
|
||||
# I2C system bus drivers (mostly embedded / system-on-chip)
|
||||
#
|
||||
# CONFIG_I2C_CBUS_GPIO is not set
|
||||
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
|
||||
# CONFIG_I2C_EMEV2 is not set
|
||||
# CONFIG_I2C_GPIO is not set
|
||||
CONFIG_I2C_LITEX=y
|
||||
# CONFIG_I2C_OCORES is not set
|
||||
# CONFIG_I2C_PCA_PLATFORM is not set
|
||||
# CONFIG_I2C_RK3X is not set
|
||||
# CONFIG_I2C_SIMTEC is not set
|
||||
# CONFIG_I2C_XILINX is not set
|
||||
|
||||
#
|
||||
# External I2C/SMBus adapter drivers
|
||||
#
|
||||
# CONFIG_I2C_PARPORT_LIGHT is not set
|
||||
# CONFIG_I2C_TAOS_EVM is not set
|
||||
|
||||
#
|
||||
# Other I2C/SMBus bus drivers
|
||||
#
|
||||
# CONFIG_I2C_SLAVE is not set
|
||||
# CONFIG_I2C_DEBUG_CORE is not set
|
||||
# CONFIG_I2C_DEBUG_ALGO is not set
|
||||
# CONFIG_I2C_DEBUG_BUS is not set
|
||||
# CONFIG_I3C is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
# CONFIG_SPI_MEM is not set
|
||||
|
||||
#
|
||||
# SPI Master Controller Drivers
|
||||
#
|
||||
# CONFIG_SPI_ALTERA is not set
|
||||
# CONFIG_SPI_AXI_SPI_ENGINE is not set
|
||||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_CADENCE is not set
|
||||
# CONFIG_SPI_DESIGNWARE is not set
|
||||
# CONFIG_SPI_GPIO is not set
|
||||
CONFIG_SPI_LITESPI=y
|
||||
# CONFIG_SPI_FSL_SPI is not set
|
||||
# CONFIG_SPI_OC_TINY is not set
|
||||
# CONFIG_SPI_ROCKCHIP is not set
|
||||
# CONFIG_SPI_SC18IS602 is not set
|
||||
# CONFIG_SPI_MXIC is not set
|
||||
# CONFIG_SPI_XCOMM is not set
|
||||
# CONFIG_SPI_XILINX is not set
|
||||
# CONFIG_SPI_ZYNQMP_GQSPI is not set
|
||||
|
||||
#
|
||||
# SPI Protocol Masters
|
||||
#
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SPI_TLE62X0 is not set
|
||||
# CONFIG_SPI_SLAVE is not set
|
||||
# CONFIG_SPMI is not set
|
||||
# CONFIG_HSI is not set
|
||||
# CONFIG_PPS is not set
|
||||
|
||||
#
|
||||
# PTP clock support
|
||||
#
|
||||
# CONFIG_PTP_1588_CLOCK is not set
|
||||
|
||||
#
|
||||
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
|
||||
#
|
||||
# CONFIG_PINCTRL is not set
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
|
||||
#
|
||||
# Memory mapped GPIO drivers
|
||||
#
|
||||
# CONFIG_GPIO_74XX_MMIO is not set
|
||||
# CONFIG_GPIO_ALTERA is not set
|
||||
# CONFIG_GPIO_CADENCE is not set
|
||||
# CONFIG_GPIO_DWAPB is not set
|
||||
# CONFIG_GPIO_FTGPIO010 is not set
|
||||
# CONFIG_GPIO_GENERIC_PLATFORM is not set
|
||||
# CONFIG_GPIO_GRGPIO is not set
|
||||
# CONFIG_GPIO_HLWD is not set
|
||||
CONFIG_GPIO_LITEX=y
|
||||
# CONFIG_GPIO_MB86S7X is not set
|
||||
# CONFIG_GPIO_MOCKUP is not set
|
||||
# CONFIG_GPIO_XILINX is not set
|
||||
|
||||
#
|
||||
# I2C GPIO expanders
|
||||
#
|
||||
# CONFIG_GPIO_ADP5588 is not set
|
||||
# CONFIG_GPIO_ADNP is not set
|
||||
# CONFIG_GPIO_MAX7300 is not set
|
||||
# CONFIG_GPIO_MAX732X is not set
|
||||
# CONFIG_GPIO_PCA953X is not set
|
||||
# CONFIG_GPIO_PCF857X is not set
|
||||
# CONFIG_GPIO_TPIC2810 is not set
|
||||
|
||||
#
|
||||
# MFD GPIO expanders
|
||||
#
|
||||
|
||||
#
|
||||
# SPI GPIO expanders
|
||||
#
|
||||
# CONFIG_GPIO_74X164 is not set
|
||||
# CONFIG_GPIO_MAX3191X is not set
|
||||
# CONFIG_GPIO_MAX7301 is not set
|
||||
# CONFIG_GPIO_MC33880 is not set
|
||||
# CONFIG_GPIO_PISOSR is not set
|
||||
# CONFIG_GPIO_XRA1403 is not set
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_AVS is not set
|
||||
# CONFIG_POWER_RESET is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
CONFIG_HWMON=y
|
||||
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||
|
||||
#
|
||||
# Native drivers
|
||||
#
|
||||
# CONFIG_SENSORS_AD7314 is not set
|
||||
# CONFIG_SENSORS_AD7414 is not set
|
||||
# CONFIG_SENSORS_AD7418 is not set
|
||||
# CONFIG_SENSORS_ADM1021 is not set
|
||||
# CONFIG_SENSORS_ADM1025 is not set
|
||||
# CONFIG_SENSORS_ADM1026 is not set
|
||||
# CONFIG_SENSORS_ADM1029 is not set
|
||||
# CONFIG_SENSORS_ADM1031 is not set
|
||||
# CONFIG_SENSORS_ADM9240 is not set
|
||||
# CONFIG_SENSORS_ADT7310 is not set
|
||||
# CONFIG_SENSORS_ADT7410 is not set
|
||||
# CONFIG_SENSORS_ADT7411 is not set
|
||||
# CONFIG_SENSORS_ADT7462 is not set
|
||||
# CONFIG_SENSORS_ADT7470 is not set
|
||||
# CONFIG_SENSORS_ADT7475 is not set
|
||||
# CONFIG_SENSORS_ASC7621 is not set
|
||||
# CONFIG_SENSORS_ASPEED is not set
|
||||
# CONFIG_SENSORS_ATXP1 is not set
|
||||
# CONFIG_SENSORS_DS620 is not set
|
||||
# CONFIG_SENSORS_DS1621 is not set
|
||||
# CONFIG_SENSORS_F71805F is not set
|
||||
# CONFIG_SENSORS_F71882FG is not set
|
||||
# CONFIG_SENSORS_F75375S is not set
|
||||
# CONFIG_SENSORS_GL518SM is not set
|
||||
# CONFIG_SENSORS_GL520SM is not set
|
||||
# CONFIG_SENSORS_G760A is not set
|
||||
# CONFIG_SENSORS_G762 is not set
|
||||
# CONFIG_SENSORS_GPIO_FAN is not set
|
||||
# CONFIG_SENSORS_HIH6130 is not set
|
||||
# CONFIG_SENSORS_IT87 is not set
|
||||
# CONFIG_SENSORS_JC42 is not set
|
||||
# CONFIG_SENSORS_POWR1220 is not set
|
||||
# CONFIG_SENSORS_LINEAGE is not set
|
||||
# CONFIG_SENSORS_LTC2945 is not set
|
||||
# CONFIG_SENSORS_LTC2990 is not set
|
||||
# CONFIG_SENSORS_LTC4151 is not set
|
||||
# CONFIG_SENSORS_LTC4215 is not set
|
||||
# CONFIG_SENSORS_LTC4222 is not set
|
||||
# CONFIG_SENSORS_LTC4245 is not set
|
||||
# CONFIG_SENSORS_LTC4260 is not set
|
||||
# CONFIG_SENSORS_LTC4261 is not set
|
||||
# CONFIG_SENSORS_MAX1111 is not set
|
||||
# CONFIG_SENSORS_MAX16065 is not set
|
||||
# CONFIG_SENSORS_MAX1619 is not set
|
||||
# CONFIG_SENSORS_MAX1668 is not set
|
||||
# CONFIG_SENSORS_MAX197 is not set
|
||||
# CONFIG_SENSORS_MAX31722 is not set
|
||||
# CONFIG_SENSORS_MAX6621 is not set
|
||||
# CONFIG_SENSORS_MAX6639 is not set
|
||||
# CONFIG_SENSORS_MAX6642 is not set
|
||||
# CONFIG_SENSORS_MAX6650 is not set
|
||||
# CONFIG_SENSORS_MAX6697 is not set
|
||||
# CONFIG_SENSORS_MAX31790 is not set
|
||||
# CONFIG_SENSORS_MCP3021 is not set
|
||||
# CONFIG_SENSORS_TC654 is not set
|
||||
# CONFIG_SENSORS_ADCXX is not set
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
# CONFIG_SENSORS_LM63 is not set
|
||||
# CONFIG_SENSORS_LM70 is not set
|
||||
# CONFIG_SENSORS_LM73 is not set
|
||||
# CONFIG_SENSORS_LM75 is not set
|
||||
# CONFIG_SENSORS_LM77 is not set
|
||||
# CONFIG_SENSORS_LM78 is not set
|
||||
# CONFIG_SENSORS_LM80 is not set
|
||||
# CONFIG_SENSORS_LM83 is not set
|
||||
# CONFIG_SENSORS_LM85 is not set
|
||||
# CONFIG_SENSORS_LM87 is not set
|
||||
# CONFIG_SENSORS_LM90 is not set
|
||||
# CONFIG_SENSORS_LM92 is not set
|
||||
# CONFIG_SENSORS_LM93 is not set
|
||||
# CONFIG_SENSORS_LM95234 is not set
|
||||
# CONFIG_SENSORS_LM95241 is not set
|
||||
# CONFIG_SENSORS_LM95245 is not set
|
||||
# CONFIG_SENSORS_PC87360 is not set
|
||||
# CONFIG_SENSORS_PC87427 is not set
|
||||
# CONFIG_SENSORS_NTC_THERMISTOR is not set
|
||||
# CONFIG_SENSORS_NCT6683 is not set
|
||||
# CONFIG_SENSORS_NCT6775 is not set
|
||||
# CONFIG_SENSORS_NCT7802 is not set
|
||||
# CONFIG_SENSORS_NCT7904 is not set
|
||||
# CONFIG_SENSORS_NPCM7XX is not set
|
||||
# CONFIG_SENSORS_OCC_P8_I2C is not set
|
||||
# CONFIG_SENSORS_PCF8591 is not set
|
||||
# CONFIG_PMBUS is not set
|
||||
# CONFIG_SENSORS_SHT15 is not set
|
||||
# CONFIG_SENSORS_SHT21 is not set
|
||||
# CONFIG_SENSORS_SHT3x is not set
|
||||
# CONFIG_SENSORS_SHTC1 is not set
|
||||
# CONFIG_SENSORS_DME1737 is not set
|
||||
# CONFIG_SENSORS_EMC1403 is not set
|
||||
# CONFIG_SENSORS_EMC2103 is not set
|
||||
# CONFIG_SENSORS_EMC6W201 is not set
|
||||
# CONFIG_SENSORS_SMSC47M1 is not set
|
||||
# CONFIG_SENSORS_SMSC47M192 is not set
|
||||
# CONFIG_SENSORS_SMSC47B397 is not set
|
||||
# CONFIG_SENSORS_STTS751 is not set
|
||||
# CONFIG_SENSORS_SMM665 is not set
|
||||
# CONFIG_SENSORS_ADC128D818 is not set
|
||||
# CONFIG_SENSORS_ADS1015 is not set
|
||||
# CONFIG_SENSORS_ADS7828 is not set
|
||||
# CONFIG_SENSORS_ADS7871 is not set
|
||||
# CONFIG_SENSORS_AMC6821 is not set
|
||||
# CONFIG_SENSORS_INA209 is not set
|
||||
# CONFIG_SENSORS_INA2XX is not set
|
||||
# CONFIG_SENSORS_INA3221 is not set
|
||||
# CONFIG_SENSORS_TC74 is not set
|
||||
# CONFIG_SENSORS_THMC50 is not set
|
||||
# CONFIG_SENSORS_TMP102 is not set
|
||||
# CONFIG_SENSORS_TMP103 is not set
|
||||
# CONFIG_SENSORS_TMP108 is not set
|
||||
# CONFIG_SENSORS_TMP401 is not set
|
||||
# CONFIG_SENSORS_TMP421 is not set
|
||||
# CONFIG_SENSORS_VT1211 is not set
|
||||
# CONFIG_SENSORS_W83773G is not set
|
||||
# CONFIG_SENSORS_W83781D is not set
|
||||
# CONFIG_SENSORS_W83791D is not set
|
||||
# CONFIG_SENSORS_W83792D is not set
|
||||
# CONFIG_SENSORS_W83793 is not set
|
||||
# CONFIG_SENSORS_W83795 is not set
|
||||
# CONFIG_SENSORS_W83L785TS is not set
|
||||
# CONFIG_SENSORS_W83L786NG is not set
|
||||
# CONFIG_SENSORS_W83627HF is not set
|
||||
# CONFIG_SENSORS_W83627EHF is not set
|
||||
# CONFIG_THERMAL is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
# CONFIG_SSB is not set
|
||||
CONFIG_BCMA_POSSIBLE=y
|
||||
# CONFIG_BCMA is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_ACT8945A is not set
|
||||
# CONFIG_MFD_AS3711 is not set
|
||||
# CONFIG_MFD_AS3722 is not set
|
||||
# CONFIG_PMIC_ADP5520 is not set
|
||||
# CONFIG_MFD_AAT2870_CORE is not set
|
||||
# CONFIG_MFD_ATMEL_FLEXCOM is not set
|
||||
# CONFIG_MFD_ATMEL_HLCDC is not set
|
||||
# CONFIG_MFD_BCM590XX is not set
|
||||
# CONFIG_MFD_BD9571MWV is not set
|
||||
# CONFIG_MFD_AXP20X_I2C is not set
|
||||
# CONFIG_MFD_MADERA is not set
|
||||
# CONFIG_PMIC_DA903X is not set
|
||||
# CONFIG_MFD_DA9052_SPI is not set
|
||||
# CONFIG_MFD_DA9052_I2C is not set
|
||||
# CONFIG_MFD_DA9055 is not set
|
||||
# CONFIG_MFD_DA9062 is not set
|
||||
# CONFIG_MFD_DA9063 is not set
|
||||
# CONFIG_MFD_DA9150 is not set
|
||||
# CONFIG_MFD_MC13XXX_SPI is not set
|
||||
# CONFIG_MFD_MC13XXX_I2C is not set
|
||||
# CONFIG_MFD_HI6421_PMIC is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_HTC_I2CPLD is not set
|
||||
# CONFIG_MFD_KEMPLD is not set
|
||||
# CONFIG_MFD_88PM800 is not set
|
||||
# CONFIG_MFD_88PM805 is not set
|
||||
# CONFIG_MFD_88PM860X is not set
|
||||
# CONFIG_MFD_MAX14577 is not set
|
||||
# CONFIG_MFD_MAX77620 is not set
|
||||
# CONFIG_MFD_MAX77686 is not set
|
||||
# CONFIG_MFD_MAX77693 is not set
|
||||
# CONFIG_MFD_MAX77843 is not set
|
||||
# CONFIG_MFD_MAX8907 is not set
|
||||
# CONFIG_MFD_MAX8925 is not set
|
||||
# CONFIG_MFD_MAX8997 is not set
|
||||
# CONFIG_MFD_MAX8998 is not set
|
||||
# CONFIG_MFD_MT6397 is not set
|
||||
# CONFIG_MFD_MENF21BMC is not set
|
||||
# CONFIG_EZX_PCAP is not set
|
||||
# CONFIG_MFD_CPCAP is not set
|
||||
# CONFIG_MFD_RETU is not set
|
||||
# CONFIG_MFD_PCF50633 is not set
|
||||
# CONFIG_MFD_RT5033 is not set
|
||||
# CONFIG_MFD_RC5T583 is not set
|
||||
# CONFIG_MFD_RK808 is not set
|
||||
# CONFIG_MFD_RN5T618 is not set
|
||||
# CONFIG_MFD_SEC_CORE is not set
|
||||
# CONFIG_MFD_SI476X_CORE is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_MFD_SKY81452 is not set
|
||||
# CONFIG_MFD_SMSC is not set
|
||||
# CONFIG_ABX500_CORE is not set
|
||||
# CONFIG_MFD_STMPE is not set
|
||||
# CONFIG_MFD_SYSCON is not set
|
||||
# CONFIG_MFD_TI_AM335X_TSCADC is not set
|
||||
# CONFIG_MFD_LP3943 is not set
|
||||
# CONFIG_MFD_LP8788 is not set
|
||||
# CONFIG_MFD_TI_LMU is not set
|
||||
# CONFIG_MFD_PALMAS is not set
|
||||
# CONFIG_TPS6105X is not set
|
||||
# CONFIG_TPS65010 is not set
|
||||
# CONFIG_TPS6507X is not set
|
||||
# CONFIG_MFD_TPS65086 is not set
|
||||
# CONFIG_MFD_TPS65090 is not set
|
||||
# CONFIG_MFD_TPS65217 is not set
|
||||
# CONFIG_MFD_TI_LP873X is not set
|
||||
# CONFIG_MFD_TI_LP87565 is not set
|
||||
# CONFIG_MFD_TPS65218 is not set
|
||||
# CONFIG_MFD_TPS6586X is not set
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
# CONFIG_MFD_WL1273_CORE is not set
|
||||
# CONFIG_MFD_LM3533 is not set
|
||||
# CONFIG_MFD_TC3589X is not set
|
||||
# CONFIG_MFD_ARIZONA_I2C is not set
|
||||
# CONFIG_MFD_ARIZONA_SPI is not set
|
||||
# CONFIG_MFD_WM8400 is not set
|
||||
# CONFIG_MFD_WM831X_I2C is not set
|
||||
# CONFIG_MFD_WM831X_SPI is not set
|
||||
# CONFIG_MFD_WM8350_I2C is not set
|
||||
# CONFIG_MFD_WM8994 is not set
|
||||
# CONFIG_MFD_ROHM_BD718XX is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
# CONFIG_RC_CORE is not set
|
||||
# CONFIG_MEDIA_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_DRM_DP_CEC is not set
|
||||
|
||||
#
|
||||
# ACP (Audio CoProcessor) Configuration
|
||||
#
|
||||
|
||||
#
|
||||
# AMD Library routines
|
||||
#
|
||||
|
||||
#
|
||||
# Frame buffer Devices
|
||||
#
|
||||
CONFIG_FB_CMDLINE=y
|
||||
CONFIG_FB_NOTIFY=y
|
||||
CONFIG_FB=y
|
||||
# CONFIG_FIRMWARE_EDID is not set
|
||||
CONFIG_FB_CFB_FILLRECT=y
|
||||
CONFIG_FB_CFB_COPYAREA=y
|
||||
CONFIG_FB_CFB_IMAGEBLIT=y
|
||||
# CONFIG_FB_FOREIGN_ENDIAN is not set
|
||||
# CONFIG_FB_MODE_HELPERS is not set
|
||||
# CONFIG_FB_TILEBLITTING is not set
|
||||
|
||||
#
|
||||
# Frame buffer hardware drivers
|
||||
#
|
||||
# CONFIG_FB_OPENCORES is not set
|
||||
# CONFIG_FB_S1D13XXX is not set
|
||||
# CONFIG_FB_IBM_GXT4500 is not set
|
||||
# CONFIG_FB_VIRTUAL is not set
|
||||
# CONFIG_FB_METRONOME is not set
|
||||
CONFIG_FB_SIMPLE=y
|
||||
# CONFIG_FB_SSD1307 is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Console display driver support
|
||||
#
|
||||
CONFIG_VGA_CONSOLE=y
|
||||
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DUMMY_CONSOLE_COLUMNS=80
|
||||
CONFIG_DUMMY_CONSOLE_ROWS=25
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_LOGO_LINUX_MONO=y
|
||||
CONFIG_LOGO_LINUX_VGA16=y
|
||||
CONFIG_LOGO_LINUX_CLUT224=y
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# HID support
|
||||
#
|
||||
CONFIG_HID=y
|
||||
# CONFIG_HID_BATTERY_STRENGTH is not set
|
||||
# CONFIG_HIDRAW is not set
|
||||
# CONFIG_UHID is not set
|
||||
CONFIG_HID_GENERIC=y
|
||||
|
||||
#
|
||||
# Special HID drivers
|
||||
#
|
||||
CONFIG_HID_A4TECH=y
|
||||
# CONFIG_HID_ACRUX is not set
|
||||
CONFIG_HID_APPLE=y
|
||||
# CONFIG_HID_AUREAL is not set
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
# CONFIG_HID_COUGAR is not set
|
||||
# CONFIG_HID_CMEDIA is not set
|
||||
CONFIG_HID_CYPRESS=y
|
||||
# CONFIG_HID_DRAGONRISE is not set
|
||||
# CONFIG_HID_EMS_FF is not set
|
||||
# CONFIG_HID_ELECOM is not set
|
||||
CONFIG_HID_EZKEY=y
|
||||
# CONFIG_HID_GEMBIRD is not set
|
||||
# CONFIG_HID_GFRM is not set
|
||||
# CONFIG_HID_KEYTOUCH is not set
|
||||
# CONFIG_HID_KYE is not set
|
||||
# CONFIG_HID_WALTOP is not set
|
||||
# CONFIG_HID_GYRATION is not set
|
||||
# CONFIG_HID_ICADE is not set
|
||||
CONFIG_HID_ITE=y
|
||||
# CONFIG_HID_JABRA is not set
|
||||
# CONFIG_HID_TWINHAN is not set
|
||||
CONFIG_HID_KENSINGTON=y
|
||||
# CONFIG_HID_LCPOWER is not set
|
||||
# CONFIG_HID_LENOVO is not set
|
||||
CONFIG_HID_LOGITECH=y
|
||||
# CONFIG_HID_LOGITECH_HIDPP is not set
|
||||
# CONFIG_LOGITECH_FF is not set
|
||||
# CONFIG_LOGIRUMBLEPAD2_FF is not set
|
||||
# CONFIG_LOGIG940_FF is not set
|
||||
# CONFIG_LOGIWHEELS_FF is not set
|
||||
# CONFIG_HID_MAGICMOUSE is not set
|
||||
# CONFIG_HID_MAYFLASH is not set
|
||||
CONFIG_HID_REDRAGON=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
# CONFIG_HID_MULTITOUCH is not set
|
||||
# CONFIG_HID_NTI is not set
|
||||
# CONFIG_HID_ORTEK is not set
|
||||
# CONFIG_HID_PANTHERLORD is not set
|
||||
# CONFIG_HID_PETALYNX is not set
|
||||
# CONFIG_HID_PICOLCD is not set
|
||||
# CONFIG_HID_PLANTRONICS is not set
|
||||
# CONFIG_HID_PRIMAX is not set
|
||||
# CONFIG_HID_SAITEK is not set
|
||||
# CONFIG_HID_SAMSUNG is not set
|
||||
# CONFIG_HID_SPEEDLINK is not set
|
||||
# CONFIG_HID_STEAM is not set
|
||||
# CONFIG_HID_STEELSERIES is not set
|
||||
# CONFIG_HID_SUNPLUS is not set
|
||||
# CONFIG_HID_RMI is not set
|
||||
# CONFIG_HID_GREENASIA is not set
|
||||
# CONFIG_HID_SMARTJOYPLUS is not set
|
||||
# CONFIG_HID_TIVO is not set
|
||||
# CONFIG_HID_TOPSEED is not set
|
||||
# CONFIG_HID_THRUSTMASTER is not set
|
||||
# CONFIG_HID_UDRAW_PS3 is not set
|
||||
# CONFIG_HID_XINMO is not set
|
||||
# CONFIG_HID_ZEROPLUS is not set
|
||||
# CONFIG_HID_ZYDACRON is not set
|
||||
# CONFIG_HID_SENSOR_HUB is not set
|
||||
# CONFIG_HID_ALPS is not set
|
||||
|
||||
#
|
||||
# I2C HID support
|
||||
#
|
||||
# CONFIG_I2C_HID is not set
|
||||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
# CONFIG_USB is not set
|
||||
|
||||
#
|
||||
# USB port drivers
|
||||
#
|
||||
|
||||
#
|
||||
# USB Physical Layer drivers
|
||||
#
|
||||
# CONFIG_NOP_USB_XCEIV is not set
|
||||
# CONFIG_USB_GPIO_VBUS is not set
|
||||
# CONFIG_USB_GADGET is not set
|
||||
# CONFIG_TYPEC is not set
|
||||
# CONFIG_USB_ROLE_SWITCH is not set
|
||||
# CONFIG_USB_ULPI_BUS is not set
|
||||
# CONFIG_UWB is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
# CONFIG_INFINIBAND is not set
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
# CONFIG_DMADEVICES is not set
|
||||
|
||||
#
|
||||
# DMABUF options
|
||||
#
|
||||
# CONFIG_SYNC_FILE is not set
|
||||
# CONFIG_AUXDISPLAY is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_VIRT_DRIVERS is not set
|
||||
CONFIG_VIRTIO_MENU=y
|
||||
# CONFIG_VIRTIO_MMIO is not set
|
||||
|
||||
#
|
||||
# Microsoft Hyper-V guest support
|
||||
#
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
|
||||
#
|
||||
# Common Clock Framework
|
||||
#
|
||||
# CONFIG_CLK_HSDK is not set
|
||||
# CONFIG_COMMON_CLK_MAX9485 is not set
|
||||
# CONFIG_COMMON_CLK_SI5351 is not set
|
||||
# CONFIG_COMMON_CLK_SI514 is not set
|
||||
# CONFIG_COMMON_CLK_SI544 is not set
|
||||
# CONFIG_COMMON_CLK_SI570 is not set
|
||||
# CONFIG_COMMON_CLK_CDCE706 is not set
|
||||
# CONFIG_COMMON_CLK_CDCE925 is not set
|
||||
# CONFIG_COMMON_CLK_CS2000_CP is not set
|
||||
# CONFIG_COMMON_CLK_VC5 is not set
|
||||
# CONFIG_HWSPINLOCK is not set
|
||||
|
||||
#
|
||||
# Clock Source drivers
|
||||
#
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
# CONFIG_ARM_TIMER_SP804 is not set
|
||||
CONFIG_RISCV_TIMER=y
|
||||
# CONFIG_MAILBOX is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
|
||||
#
|
||||
# Generic IOMMU Pagetable Support
|
||||
#
|
||||
|
||||
#
|
||||
# Remoteproc drivers
|
||||
#
|
||||
# CONFIG_REMOTEPROC is not set
|
||||
|
||||
#
|
||||
# Rpmsg drivers
|
||||
#
|
||||
# CONFIG_RPMSG_VIRTIO is not set
|
||||
# CONFIG_SOUNDWIRE is not set
|
||||
|
||||
#
|
||||
# SOC (System On Chip) specific Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Amlogic SoC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Broadcom SoC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# NXP/Freescale QorIQ SoC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# i.MX SoC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Qualcomm SoC drivers
|
||||
#
|
||||
# CONFIG_SOC_TI is not set
|
||||
|
||||
#
|
||||
# Xilinx SoC drivers
|
||||
#
|
||||
# CONFIG_XILINX_VCU is not set
|
||||
# CONFIG_PM_DEVFREQ is not set
|
||||
# CONFIG_EXTCON is not set
|
||||
# CONFIG_MEMORY is not set
|
||||
# CONFIG_IIO is not set
|
||||
# CONFIG_PWM is not set
|
||||
|
||||
#
|
||||
# IRQ chip support
|
||||
#
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_ARM_GIC_MAX_NR=1
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
# CONFIG_IPACK_BUS is not set
|
||||
# CONFIG_RESET_CONTROLLER is not set
|
||||
# CONFIG_FMC is not set
|
||||
|
||||
#
|
||||
# PHY Subsystem
|
||||
#
|
||||
# CONFIG_GENERIC_PHY is not set
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# CONFIG_PHY_CADENCE_DP is not set
|
||||
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
|
||||
# CONFIG_PHY_PXA_28NM_HSIC is not set
|
||||
# CONFIG_PHY_PXA_28NM_USB2 is not set
|
||||
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
|
||||
# CONFIG_POWERCAP is not set
|
||||
# CONFIG_MCB is not set
|
||||
# CONFIG_RAS is not set
|
||||
|
||||
#
|
||||
# Android
|
||||
#
|
||||
# CONFIG_ANDROID is not set
|
||||
# CONFIG_LIBNVDIMM is not set
|
||||
# CONFIG_DAX is not set
|
||||
# CONFIG_NVMEM is not set
|
||||
|
||||
#
|
||||
# HW tracing support
|
||||
#
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_TH is not set
|
||||
# CONFIG_FPGA is not set
|
||||
# CONFIG_FSI is not set
|
||||
# CONFIG_SIOX is not set
|
||||
# CONFIG_SLIMBUS is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_BTRFS_FS is not set
|
||||
# CONFIG_NILFS2_FS is not set
|
||||
# CONFIG_F2FS_FS is not set
|
||||
# CONFIG_FS_DAX is not set
|
||||
CONFIG_EXPORTFS=y
|
||||
# CONFIG_EXPORTFS_BLOCK_OPS is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
# CONFIG_FS_ENCRYPTION is not set
|
||||
CONFIG_FSNOTIFY=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_FANOTIFY is not set
|
||||
# CONFIG_QUOTA is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
# CONFIG_OVERLAY_FS is not set
|
||||
|
||||
#
|
||||
# Caches
|
||||
#
|
||||
# CONFIG_FSCACHE is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
# CONFIG_PROC_CHILDREN is not set
|
||||
CONFIG_KERNFS=y
|
||||
CONFIG_SYSFS=y
|
||||
# CONFIG_TMPFS is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
CONFIG_MISC_FILESYSTEMS=y
|
||||
# CONFIG_ORANGEFS_FS is not set
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_SQUASHFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_QNX6FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_PSTORE is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
# CONFIG_NFS_FS is not set
|
||||
# CONFIG_NFSD is not set
|
||||
# CONFIG_CEPH_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
# CONFIG_NLS is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
# CONFIG_STATIC_USERMODEHELPER is not set
|
||||
CONFIG_DEFAULT_SECURITY_DAC=y
|
||||
CONFIG_DEFAULT_SECURITY=""
|
||||
CONFIG_CRYPTO=y
|
||||
|
||||
#
|
||||
# Crypto core or helper
|
||||
#
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_ALGAPI2=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_BLKCIPHER2=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_RNG_DEFAULT=y
|
||||
CONFIG_CRYPTO_AKCIPHER2=y
|
||||
CONFIG_CRYPTO_KPP2=y
|
||||
CONFIG_CRYPTO_ACOMP2=y
|
||||
# CONFIG_CRYPTO_RSA is not set
|
||||
# CONFIG_CRYPTO_DH is not set
|
||||
# CONFIG_CRYPTO_ECDH is not set
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
# CONFIG_CRYPTO_USER is not set
|
||||
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
|
||||
# CONFIG_CRYPTO_GF128MUL is not set
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_WORKQUEUE=y
|
||||
# CONFIG_CRYPTO_CRYPTD is not set
|
||||
# CONFIG_CRYPTO_AUTHENC is not set
|
||||
|
||||
#
|
||||
# Authenticated Encryption with Associated Data
|
||||
#
|
||||
# CONFIG_CRYPTO_CCM is not set
|
||||
# CONFIG_CRYPTO_GCM is not set
|
||||
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
|
||||
# CONFIG_CRYPTO_AEGIS128 is not set
|
||||
# CONFIG_CRYPTO_AEGIS128L is not set
|
||||
# CONFIG_CRYPTO_AEGIS256 is not set
|
||||
# CONFIG_CRYPTO_MORUS640 is not set
|
||||
# CONFIG_CRYPTO_MORUS1280 is not set
|
||||
# CONFIG_CRYPTO_SEQIV is not set
|
||||
CONFIG_CRYPTO_ECHAINIV=y
|
||||
|
||||
#
|
||||
# Block modes
|
||||
#
|
||||
# CONFIG_CRYPTO_CBC is not set
|
||||
# CONFIG_CRYPTO_CFB is not set
|
||||
# CONFIG_CRYPTO_CTR is not set
|
||||
# CONFIG_CRYPTO_CTS is not set
|
||||
# CONFIG_CRYPTO_ECB is not set
|
||||
# CONFIG_CRYPTO_LRW is not set
|
||||
# CONFIG_CRYPTO_OFB is not set
|
||||
# CONFIG_CRYPTO_PCBC is not set
|
||||
# CONFIG_CRYPTO_XTS is not set
|
||||
# CONFIG_CRYPTO_KEYWRAP is not set
|
||||
# CONFIG_CRYPTO_ADIANTUM is not set
|
||||
|
||||
#
|
||||
# Hash modes
|
||||
#
|
||||
# CONFIG_CRYPTO_CMAC is not set
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
# CONFIG_CRYPTO_XCBC is not set
|
||||
# CONFIG_CRYPTO_VMAC is not set
|
||||
|
||||
#
|
||||
# Digest
|
||||
#
|
||||
# CONFIG_CRYPTO_CRC32C is not set
|
||||
# CONFIG_CRYPTO_CRC32 is not set
|
||||
# CONFIG_CRYPTO_CRCT10DIF is not set
|
||||
# CONFIG_CRYPTO_GHASH is not set
|
||||
# CONFIG_CRYPTO_POLY1305 is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
# CONFIG_CRYPTO_MD5 is not set
|
||||
# CONFIG_CRYPTO_MICHAEL_MIC is not set
|
||||
# CONFIG_CRYPTO_RMD128 is not set
|
||||
# CONFIG_CRYPTO_RMD160 is not set
|
||||
# CONFIG_CRYPTO_RMD256 is not set
|
||||
# CONFIG_CRYPTO_RMD320 is not set
|
||||
# CONFIG_CRYPTO_SHA1 is not set
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
# CONFIG_CRYPTO_SHA512 is not set
|
||||
# CONFIG_CRYPTO_SHA3 is not set
|
||||
# CONFIG_CRYPTO_SM3 is not set
|
||||
# CONFIG_CRYPTO_STREEBOG is not set
|
||||
# CONFIG_CRYPTO_TGR192 is not set
|
||||
# CONFIG_CRYPTO_WP512 is not set
|
||||
|
||||
#
|
||||
# Ciphers
|
||||
#
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_AES_TI is not set
|
||||
# CONFIG_CRYPTO_ANUBIS is not set
|
||||
# CONFIG_CRYPTO_ARC4 is not set
|
||||
# CONFIG_CRYPTO_BLOWFISH is not set
|
||||
# CONFIG_CRYPTO_CAMELLIA is not set
|
||||
# CONFIG_CRYPTO_CAST5 is not set
|
||||
# CONFIG_CRYPTO_CAST6 is not set
|
||||
# CONFIG_CRYPTO_DES is not set
|
||||
# CONFIG_CRYPTO_FCRYPT is not set
|
||||
# CONFIG_CRYPTO_KHAZAD is not set
|
||||
# CONFIG_CRYPTO_SALSA20 is not set
|
||||
# CONFIG_CRYPTO_CHACHA20 is not set
|
||||
# CONFIG_CRYPTO_SEED is not set
|
||||
# CONFIG_CRYPTO_SERPENT is not set
|
||||
# CONFIG_CRYPTO_SM4 is not set
|
||||
# CONFIG_CRYPTO_TEA is not set
|
||||
# CONFIG_CRYPTO_TWOFISH is not set
|
||||
|
||||
#
|
||||
# Compression
|
||||
#
|
||||
# CONFIG_CRYPTO_DEFLATE is not set
|
||||
# CONFIG_CRYPTO_LZO is not set
|
||||
# CONFIG_CRYPTO_842 is not set
|
||||
# CONFIG_CRYPTO_LZ4 is not set
|
||||
# CONFIG_CRYPTO_LZ4HC is not set
|
||||
# CONFIG_CRYPTO_ZSTD is not set
|
||||
|
||||
#
|
||||
# Random Number Generation
|
||||
#
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DRBG_MENU=y
|
||||
CONFIG_CRYPTO_DRBG_HMAC=y
|
||||
# CONFIG_CRYPTO_DRBG_HASH is not set
|
||||
CONFIG_CRYPTO_DRBG=y
|
||||
CONFIG_CRYPTO_JITTERENTROPY=y
|
||||
# CONFIG_CRYPTO_USER_API_HASH is not set
|
||||
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
|
||||
# CONFIG_CRYPTO_USER_API_RNG is not set
|
||||
# CONFIG_CRYPTO_USER_API_AEAD is not set
|
||||
CONFIG_CRYPTO_HW=y
|
||||
# CONFIG_CRYPTO_DEV_CCREE is not set
|
||||
|
||||
#
|
||||
# Certificates for signature checking
|
||||
#
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_NET_UTILS=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC32_SELFTEST is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
# CONFIG_CRC32_SLICEBY4 is not set
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
# CONFIG_CRC32_BIT is not set
|
||||
# CONFIG_CRC64 is not set
|
||||
# CONFIG_CRC4 is not set
|
||||
# CONFIG_CRC7 is not set
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
# CONFIG_CRC8 is not set
|
||||
# CONFIG_RANDOM32_SELFTEST is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_LZ4_DECOMPRESS=y
|
||||
CONFIG_XZ_DEC=y
|
||||
CONFIG_XZ_DEC_X86=y
|
||||
CONFIG_XZ_DEC_POWERPC=y
|
||||
CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
CONFIG_DECOMPRESS_BZIP2=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DECOMPRESS_XZ=y
|
||||
CONFIG_DECOMPRESS_LZO=y
|
||||
CONFIG_DECOMPRESS_LZ4=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_DQL=y
|
||||
CONFIG_NLATTR=y
|
||||
CONFIG_GENERIC_ATOMIC64=y
|
||||
# CONFIG_CORDIC is not set
|
||||
# CONFIG_DDR is not set
|
||||
# CONFIG_IRQ_POLL is not set
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_SBITMAP=y
|
||||
# CONFIG_STRING_SELFTEST is not set
|
||||
CONFIG_GENERIC_LIB_ASHLDI3=y
|
||||
CONFIG_GENERIC_LIB_ASHRDI3=y
|
||||
CONFIG_GENERIC_LIB_LSHRDI3=y
|
||||
CONFIG_GENERIC_LIB_UCMPDI2=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
|
||||
#
|
||||
# printk and dmesg options
|
||||
#
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
|
||||
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
|
||||
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
|
||||
|
||||
#
|
||||
# Compile-time checks and compiler options
|
||||
#
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_SECTION_MISMATCH is not set
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
|
||||
#
|
||||
# Memory Debugging
|
||||
#
|
||||
# CONFIG_PAGE_EXTENSION is not set
|
||||
# CONFIG_PAGE_POISONING is not set
|
||||
# CONFIG_SLUB_DEBUG_ON is not set
|
||||
# CONFIG_SLUB_STATS is not set
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_CC_HAS_KASAN_GENERIC=y
|
||||
CONFIG_KASAN_STACK=1
|
||||
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
|
||||
|
||||
#
|
||||
# Debug Lockups and Hangs
|
||||
#
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_DEBUG_TIMEKEEPING is not set
|
||||
|
||||
#
|
||||
# Lock Debugging (spinlocks, mutexes, etc...)
|
||||
#
|
||||
# CONFIG_WW_MUTEX_SELFTEST is not set
|
||||
# CONFIG_STACKTRACE is not set
|
||||
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
|
||||
#
|
||||
# RCU Debugging
|
||||
#
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_DMA_API_DEBUG is not set
|
||||
CONFIG_RUNTIME_TESTING_MENU=y
|
||||
# CONFIG_ATOMIC64_SELFTEST is not set
|
||||
# CONFIG_TEST_HEXDUMP is not set
|
||||
# CONFIG_TEST_STRING_HELPERS is not set
|
||||
# CONFIG_TEST_KSTRTOX is not set
|
||||
# CONFIG_TEST_PRINTF is not set
|
||||
# CONFIG_TEST_BITMAP is not set
|
||||
# CONFIG_TEST_BITFIELD is not set
|
||||
# CONFIG_TEST_UUID is not set
|
||||
# CONFIG_TEST_XARRAY is not set
|
||||
# CONFIG_TEST_OVERFLOW is not set
|
||||
# CONFIG_TEST_RHASHTABLE is not set
|
||||
# CONFIG_TEST_HASH is not set
|
||||
# CONFIG_TEST_IDA is not set
|
||||
# CONFIG_FIND_BIT_BENCHMARK is not set
|
||||
# CONFIG_TEST_FIRMWARE is not set
|
||||
# CONFIG_TEST_SYSCTL is not set
|
||||
# CONFIG_TEST_UDELAY is not set
|
||||
# CONFIG_TEST_MEMCAT_P is not set
|
||||
# CONFIG_MEMTEST is not set
|
||||
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
@ -0,0 +1,82 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-1fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
# ext4
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_USE_FOR_EXT2=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRC16=y
|
||||
|
||||
# mmc
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=y
|
||||
CONFIG_PWRSEQ_SIMPLE=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=8
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
# ext4
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_USE_FOR_EXT2=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRC16=y
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=2
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
|
||||
@ -0,0 +1,55 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,83 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
# ext4
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_USE_FOR_EXT2=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRC16=y
|
||||
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
|
||||
@ -0,0 +1,82 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-1fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
# ext4
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_USE_FOR_EXT2=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRC16=y
|
||||
|
||||
# mmc
|
||||
CONFIG_MMC=y
|
||||
CONFIG_PWRSEQ_EMMC=y
|
||||
CONFIG_PWRSEQ_SIMPLE=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=8
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC7=y
|
||||
|
||||
@ -0,0 +1,57 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
@ -0,0 +1,62 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
CONFIG_LOCALVERSION="-0fstrellis"
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
|
||||
# ext4
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_USE_FOR_EXT2=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRC16=y
|
||||
|
||||
@ -0,0 +1,260 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import os
|
||||
|
||||
from litex.soc.integration.builder import Builder
|
||||
|
||||
from soc_linux import SoCLinux
|
||||
|
||||
kB = 1024
|
||||
|
||||
# Board definition----------------------------------------------------------------------------------
|
||||
|
||||
class Board:
|
||||
def __init__(self, soc_cls, soc_capabilities):
|
||||
self.soc_cls = soc_cls
|
||||
self.soc_capabilities = soc_capabilities
|
||||
|
||||
def load(self):
|
||||
raise NotImplementedError
|
||||
|
||||
def flash(self):
|
||||
raise NotImplementedError
|
||||
|
||||
# Arty support -------------------------------------------------------------------------------------
|
||||
|
||||
class Arty(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import arty
|
||||
Board.__init__(self, arty.EthernetSoC, {"serial", "ethernet", "spiflash", "leds", "switches", "spi", "i2c", "xadc"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_xilinx.cfg")
|
||||
prog.load_bitstream("build/arty/gateware/top.bit")
|
||||
|
||||
def flash(self):
|
||||
flash_regions = {
|
||||
"build/arty/gateware/top.bin": "0x00000000", # FPGA image: loaded at startup
|
||||
"buildroot/Image": "0x00400000", # Linux Image: copied to 0xc0000000 by bios
|
||||
"buildroot/rootfs.cpio": "0x00800000", # File System: copied to 0xc0800000 by bios
|
||||
"buildroot/rv32.dtb": "0x00f00000", # Device tree: copied to 0xc1000000 by bios
|
||||
"emulator/emulator.bin": "0x00f80000", # MM Emulator: copied to 0x20000000 by bios
|
||||
}
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_xilinx.cfg",
|
||||
flash_proxy_basename="prog/bscan_spi_xc7a35t.bit")
|
||||
prog.set_flash_proxy_dir(".")
|
||||
for filename, base in flash_regions.items():
|
||||
base = int(base, 16)
|
||||
print("Flashing {} at 0x{:08x}".format(filename, base))
|
||||
prog.flash(base, filename)
|
||||
|
||||
# NeTV2 support ------------------------------------------------------------------------------------
|
||||
|
||||
class NeTV2(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import netv2
|
||||
Board.__init__(self, netv2.EthernetSoC, {"serial", "ethernet", "framebuffer", "spiflash", "leds", "xadc"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_netv2_rpi.cfg")
|
||||
prog.load_bitstream("build/netv2/gateware/top.bit")
|
||||
|
||||
# Genesys2 support ---------------------------------------------------------------------------------
|
||||
|
||||
class Genesys2(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import genesys2
|
||||
Board.__init__(self, genesys2.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/genesys2/gateware/top.bit")
|
||||
|
||||
# KCU105 support -----------------------------------------------------------------------------------
|
||||
|
||||
class KCU105(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import kcu105
|
||||
Board.__init__(self, kcu105.EthernetSoC, {"serial", "ethernet"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/kcu105/gateware/top.bit")
|
||||
|
||||
|
||||
# Nexys4DDR support --------------------------------------------------------------------------------
|
||||
|
||||
class Nexys4DDR(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import nexys4ddr
|
||||
Board.__init__(self, nexys4ddr.EthernetSoC, {"serial", "ethernet"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/nexys4ddr/gateware/top.bit")
|
||||
|
||||
# NexysVideo support --------------------------------------------------------------------------------
|
||||
|
||||
class NexysVideo(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import nexys_video
|
||||
Board.__init__(self, nexys_video.EthernetSoC, {"serial", "framebuffer"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/nexys_video/gateware/top.bit")
|
||||
|
||||
# MiniSpartan6 support -----------------------------------------------------------------------------
|
||||
|
||||
class MiniSpartan6(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import minispartan6
|
||||
Board.__init__(self, minispartan6.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
os.system("xc3sprog -c ftdi build/minispartan6/gateware/top.bit")
|
||||
|
||||
|
||||
# Versa ECP5 support -------------------------------------------------------------------------------
|
||||
|
||||
class VersaECP5(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import versa_ecp5
|
||||
Board.__init__(self, versa_ecp5.EthernetSoC, {"serial", "ethernet", "spiflash"})
|
||||
|
||||
def load(self):
|
||||
os.system("openocd -f prog/ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/versa_ecp5/gateware/top.svf; exit\"")
|
||||
|
||||
# ULX3S support ------------------------------------------------------------------------------------
|
||||
|
||||
class ULX3S(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import ulx3s
|
||||
Board.__init__(self, ulx3s.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
os.system("ujprog build/ulx3s/gateware/top.svf")
|
||||
|
||||
# TrellisBoard support ------------------------------------------------------------------------------------
|
||||
|
||||
class Trellis(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import trellisboard
|
||||
Board.__init__(self, trellisboard.EthernetSoC, {"serial", "ethernet"})
|
||||
|
||||
def load(self):
|
||||
os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
|
||||
|
||||
# De0Nano support ------------------------------------------------------------------------------------
|
||||
|
||||
class De0Nano(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import de0nano
|
||||
Board.__init__(self, de0nano.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.altera import USBBlaster
|
||||
prog = USBBlaster()
|
||||
prog.load_bitstream("build/de0nano/gateware/top.sof")
|
||||
|
||||
# Main ---------------------------------------------------------------------------------------------
|
||||
|
||||
supported_boards = {
|
||||
# Xilinx
|
||||
"arty": Arty,
|
||||
"netv2": NeTV2,
|
||||
"genesys2": Genesys2,
|
||||
"kcu105": KCU105,
|
||||
"nexys4ddr": Nexys4DDR,
|
||||
"nexys_video": NexysVideo,
|
||||
"minispartan6": MiniSpartan6,
|
||||
# Lattice
|
||||
"versa_ecp5": VersaECP5,
|
||||
"ulx3s": ULX3S,
|
||||
"trellisboard": Trellis,
|
||||
# Altera/Intel
|
||||
"de0nano": De0Nano,
|
||||
}
|
||||
|
||||
def main():
|
||||
description = "Linux on LiteX-VexRiscv\n\n"
|
||||
description += "Available boards:\n"
|
||||
for name in supported_boards.keys():
|
||||
description += "- " + name + "\n"
|
||||
parser = argparse.ArgumentParser(description=description, formatter_class=argparse.RawTextHelpFormatter)
|
||||
parser.add_argument("--board", required=True, help="FPGA board")
|
||||
parser.add_argument("--build", action="store_true", help="build bitstream")
|
||||
parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)")
|
||||
parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)")
|
||||
parser.add_argument("--local-ip", default="192.168.1.50", help="local IP address")
|
||||
parser.add_argument("--remote-ip", default="192.168.1.100", help="remote IP address of TFTP server")
|
||||
parser.add_argument("--spi-bpw", type=int, default=8, help="Bits per word for SPI controller")
|
||||
parser.add_argument("--spi-sck-freq", type=int, default=1e6, help="SPI clock frequency")
|
||||
args = parser.parse_args()
|
||||
|
||||
if args.board == "all":
|
||||
board_names = list(supported_boards.keys())
|
||||
else:
|
||||
board_names = [args.board]
|
||||
for board_name in board_names:
|
||||
board = supported_boards[board_name]()
|
||||
soc_kwargs = {}
|
||||
if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
|
||||
soc_kwargs["toolchain"] = "trellis"
|
||||
soc_kwargs["cpu_variant"] = "linux+no-dsp"
|
||||
soc = SoCLinux(board.soc_cls, **soc_kwargs)
|
||||
if "spiflash" in board.soc_capabilities:
|
||||
soc.add_spi_flash()
|
||||
soc.add_constant("SPIFLASH_PAGE_SIZE", board.SPIFLASH_PAGE_SIZE)
|
||||
soc.add_constant("SPIFLASH_SECTOR_SIZE", board.SPIFLASH_SECTOR_SIZE)
|
||||
if "ethernet" in board.soc_capabilities:
|
||||
soc.configure_ethernet(local_ip=args.local_ip, remote_ip=args.remote_ip)
|
||||
if "leds" in board.soc_capabilities:
|
||||
soc.add_leds()
|
||||
if "switches" in board.soc_capabilities:
|
||||
soc.add_switches()
|
||||
if "spi" in board.soc_capabilities:
|
||||
soc.add_spi(args.spi_bpw, args.spi_sck_freq)
|
||||
if "i2c" in board.soc_capabilities:
|
||||
soc.add_i2c()
|
||||
if "xadc" in board.soc_capabilities:
|
||||
soc.add_xadc()
|
||||
if "framebuffer" in board.soc_capabilities:
|
||||
soc.add_framebuffer()
|
||||
soc.configure_boot()
|
||||
|
||||
build_dir = os.path.join("build", board_name)
|
||||
if args.build:
|
||||
builder = Builder(soc, output_dir=build_dir,
|
||||
csr_json=os.path.join(build_dir, "csr.json"))
|
||||
else:
|
||||
builder = Builder(soc, output_dir="build/" + board_name,
|
||||
compile_software=False, compile_gateware=False,
|
||||
csr_json=os.path.join(build_dir, "csr.json"))
|
||||
builder.build()
|
||||
|
||||
soc.generate_dts(board_name)
|
||||
soc.compile_dts(board_name)
|
||||
|
||||
if args.load:
|
||||
board.load()
|
||||
|
||||
if args.flash:
|
||||
board.flash()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -0,0 +1,6 @@
|
||||
Linux on LiteX-Vexriscv
|
||||
|
||||
32-bit VexRiscv CPU with MMU integrated in a LiteX SoC
|
||||
|
||||
Fork Sand Build
|
||||
|
||||
@ -0,0 +1,53 @@
|
||||
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
|
||||
|
||||
# Architecture
|
||||
CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
|
||||
CONFIG_ARCH_RV32I=y
|
||||
CONFIG_RISCV_ISA_M=y
|
||||
CONFIG_RISCV_ISA_A=y
|
||||
CONFIG_RISCV_ISA_C=n
|
||||
CONFIG_SIFIVE_PLIC=y
|
||||
CONFIG_FPU=n
|
||||
CONFIG_SMP=n
|
||||
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_LZ4=y
|
||||
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_VENDOR_LITEX=y
|
||||
CONFIG_LITEX_LITEETH=y
|
||||
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
||||
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
|
||||
CONFIG_SERIAL_LITEUART=y
|
||||
CONFIG_SERIAL_LITEUART_CONSOLE=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LITEX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_LITESPI=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_LITEX=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_SENSORS_LITEX_HWMON=y
|
||||
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_LOGO=y
|
||||
@ -0,0 +1,44 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
# Extra packages
|
||||
#BR2_PACKAGE_DHRYSTONE=y
|
||||
#BR2_PACKAGE_MICROPYTHON=y
|
||||
#BR2_PACKAGE_SPIDEV_TEST=y
|
||||
@ -0,0 +1,104 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
|
||||
# lshw
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
#BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
#BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
#BR2_INSTALL_LIBSTDCPP=y
|
||||
#BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
#BR2_PACKAGE_BZIP2=y
|
||||
#BR2_PACKAGE_BINUTILS=y
|
||||
#BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
#BR2_PACKAGE_GIT=y
|
||||
#BR2_PACKAGE_LIBTOOL=y
|
||||
#BR2_PACKAGE_MAKE=y
|
||||
|
||||
@ -0,0 +1,80 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# lshw
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
@ -0,0 +1,139 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# lshw
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
# Moar
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_FLEX=y
|
||||
BR2_PACKAGE_GETTEXT=y
|
||||
BR2_PACKAGE_HAS_GETTEXT=y
|
||||
BR2_PACKAGE_PROVIDES_GETTEXT="gettext-tiny"
|
||||
BR2_PACKAGE_GETTEXT_TINY=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
BR2_PACKAGE_PKGCONF=y
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
BR2_PACKAGE_LIBPCAP=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_HAVEGED=y
|
||||
BR2_PACKAGE_LINKS=y
|
||||
|
||||
# nginx
|
||||
BR2_PACKAGE_NGINX=y
|
||||
BR2_PACKAGE_NGINX_HTTP=y
|
||||
BR2_PACKAGE_NGINX_HTTP_CHARSET_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_GZIP_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SSI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_USERID_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_ACCESS_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_AUTH_BASIC_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_AUTOINDEX_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_GEO_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_MAP_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SPLIT_CLIENTS_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_REFERER_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_REWRITE_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_PROXY_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_MEMCACHED_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_LIMIT_CONN_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_LIMIT_REQ_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_EMPTY_GIF_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_BROWSER_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_IP_HASH_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_LEAST_CONN_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_KEEPALIVE_MODULE=y
|
||||
BR2_PACKAGE_NGINX_ADD_MODULES=""
|
||||
|
||||
BR2_PACKAGE_TCPDUMP=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
@ -0,0 +1,130 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# lshw
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
# Moar
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_FLEX=y
|
||||
BR2_PACKAGE_GETTEXT=y
|
||||
BR2_PACKAGE_HAS_GETTEXT=y
|
||||
BR2_PACKAGE_PROVIDES_GETTEXT="gettext-tiny"
|
||||
BR2_PACKAGE_GETTEXT_TINY=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
BR2_PACKAGE_PKGCONF=y
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
BR2_PACKAGE_LIBPCAP=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_HAVEGED=y
|
||||
BR2_PACKAGE_LINKS=y
|
||||
|
||||
# nginx
|
||||
BR2_PACKAGE_NGINX=y
|
||||
BR2_PACKAGE_NGINX_HTTP=y
|
||||
BR2_PACKAGE_NGINX_HTTP_CHARSET_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_GZIP_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SSI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_USERID_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_ACCESS_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_AUTH_BASIC_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_AUTOINDEX_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_GEO_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_MAP_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SPLIT_CLIENTS_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_REFERER_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_REWRITE_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_PROXY_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_FASTCGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UWSGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_SCGI_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_MEMCACHED_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_LIMIT_CONN_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_LIMIT_REQ_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_EMPTY_GIF_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_BROWSER_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_IP_HASH_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_LEAST_CONN_MODULE=y
|
||||
BR2_PACKAGE_NGINX_HTTP_UPSTREAM_KEEPALIVE_MODULE=y
|
||||
BR2_PACKAGE_NGINX_ADD_MODULES=""
|
||||
|
||||
BR2_PACKAGE_TCPDUMP=y
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
|
||||
@ -0,0 +1,104 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
BR2_PACKAGE_BZIP2=y
|
||||
BR2_PACKAGE_BINUTILS=y
|
||||
BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
BR2_PACKAGE_GIT=y
|
||||
BR2_PACKAGE_LIBTOOL=y
|
||||
BR2_PACKAGE_MAKE=y
|
||||
|
||||
# lshw
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
@ -0,0 +1,96 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
#BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
#BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
#BR2_INSTALL_LIBSTDCPP=y
|
||||
#BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
#BR2_PACKAGE_BZIP2=y
|
||||
#BR2_PACKAGE_BINUTILS=y
|
||||
#BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
#BR2_PACKAGE_GIT=y
|
||||
#BR2_PACKAGE_LIBTOOL=y
|
||||
#BR2_PACKAGE_MAKE=y
|
||||
|
||||
@ -0,0 +1,98 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
#BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
#BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
#BR2_INSTALL_LIBSTDCPP=y
|
||||
#BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
#BR2_PACKAGE_BZIP2=y
|
||||
#BR2_PACKAGE_BINUTILS=y
|
||||
#BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
#BR2_PACKAGE_GIT=y
|
||||
#BR2_PACKAGE_LIBTOOL=y
|
||||
#BR2_PACKAGE_MAKE=y
|
||||
|
||||
@ -0,0 +1,106 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=n
|
||||
|
||||
#BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
#BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
|
||||
#BR2_INSTALL_LIBSTDCPP=y
|
||||
#BR2_TOOLCHAIN_HAS_FORTRAN=y
|
||||
#BR2_PACKAGE_BZIP2=y
|
||||
#BR2_PACKAGE_BINUTILS=y
|
||||
#BR2_PACKAGE_BINUTILS_TARGET=y
|
||||
#BR2_PACKAGE_GIT=y
|
||||
#BR2_PACKAGE_LIBTOOL=y
|
||||
#BR2_PACKAGE_MAKE=y
|
||||
|
||||
# lshw
|
||||
BR2_TOOLCHAIN_BUILDROOT_CXX=y
|
||||
BR2_INSTALL_LIBSTDCPP=y
|
||||
BR2_PACKAGE_HWDATA=y
|
||||
BR2_PACKAGE_HWDATA_PCI_IDS=y
|
||||
BR2_PACKAGE_HWDATA_USB_IDS=y
|
||||
BR2_PACKAGE_LSHW=y
|
||||
|
||||
@ -0,0 +1,84 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
#BR2_PACKAGE_SSHFS=y
|
||||
#BR2_PACKAGE_OPENSSL=y
|
||||
#BR2_PACKAGE_LIBOPENSSL=y
|
||||
#BR2_PACKAGE_HAS_OPENSSL=y
|
||||
#BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
#BR2_PACKAGE_LIBFUSE=y
|
||||
#BR2_PACKAGE_LIBFFI=y
|
||||
#BR2_PACKAGE_LIBGLIB2=y
|
||||
#BR2_PACKAGE_PCRE=y
|
||||
#BR2_PACKAGE_PCRE_UTF=y
|
||||
#BR2_PACKAGE_PCRE_UCP=y
|
||||
#BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
# nbd
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_NBD=y
|
||||
BR2_PACKAGE_NBD_CLIENT=y
|
||||
|
||||
#BR2_PACKAGE_MACCHANGER=y
|
||||
|
||||
#BR2_PACKAGE_HAVEGED=y
|
||||
@ -0,0 +1,58 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
# Extra packages
|
||||
#BR2_PACKAGE_DHRYSTONE=y
|
||||
#BR2_PACKAGE_MICROPYTHON=y
|
||||
#BR2_PACKAGE_SPIDEV_TEST=y
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
|
||||
@ -0,0 +1,73 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
|
||||
#BR2_PACKAGE_DROPBEAR=y
|
||||
#BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
#BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
#BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
#BR2_PACKAGE_MMC_UTILS=y
|
||||
BR2_PACKAGE_SSHFS=y
|
||||
BR2_PACKAGE_OPENSSL=y
|
||||
BR2_PACKAGE_LIBOPENSSL=y
|
||||
BR2_PACKAGE_HAS_OPENSSL=y
|
||||
BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
BR2_PACKAGE_LIBFUSE=y
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_OPENSSH=y
|
||||
#BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
#
|
||||
# Target options
|
||||
#
|
||||
BR2_riscv=y
|
||||
BR2_RISCV_32=y
|
||||
|
||||
#
|
||||
# Instruction Set Extensions
|
||||
#
|
||||
BR2_riscv_custom=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVM=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVA=y
|
||||
BR2_RISCV_ISA_CUSTOM_RVC=n
|
||||
BR2_RISCV_ABI_ILP32=y
|
||||
|
||||
# XXX fs-trellisboard patches
|
||||
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/patches"
|
||||
|
||||
# GCC
|
||||
BR2_GCC_VERSION_8_X=y
|
||||
BR2_GCC_VERSION="8.3.0"
|
||||
|
||||
# System
|
||||
BR2_TARGET_GENERIC_GETTY=y
|
||||
BR2_TARGET_GENERIC_GETTY_PORT="console"
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_CPIO=y
|
||||
|
||||
# Kernel
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0=y
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.0.13"
|
||||
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
|
||||
# XXX Linux config file
|
||||
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/linux-fstrellis.config"
|
||||
BR2_LINUX_KERNEL_IMAGE=y
|
||||
|
||||
# rootfs customisation
|
||||
# XXX
|
||||
BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_LITEX_VEXRISCV_PATH)/board/litex_vexriscv/rootfs_overlay"
|
||||
|
||||
BR2_PACKAGE_ZLIB=y
|
||||
BR2_PACKAGE_LIBZLIB=y
|
||||
BR2_PACKAGE_HAS_ZLIB=y
|
||||
BR2_PACKAGE_PROVIDES_ZLIB="libzlib"
|
||||
BR2_PACKAGE_LIBTOMCRYPT=y
|
||||
BR2_PACKAGE_LIBTOMMATH=y
|
||||
BR2_PACKAGE_DROPBEAR=y
|
||||
BR2_PACKAGE_DROPBEAR_CLIENT=y
|
||||
BR2_PACKAGE_DROPBEAR_LOCALOPTIONS_FILE=""
|
||||
BR2_PACKAGE_DROPBEAR_SMALL=y
|
||||
|
||||
BR2_TARGET_GENERIC_HOSTNAME="trellisboard"
|
||||
BR2_TARGET_GENERIC_ISSUE="Welcome to TrellisBoard"
|
||||
BR2_TARGET_GENERIC_ROOT_PASSWD="password"
|
||||
BR2_PACKAGE_MMC_UTILS=y
|
||||
BR2_PACKAGE_SSHFS=y
|
||||
BR2_PACKAGE_OPENSSL=y
|
||||
BR2_PACKAGE_LIBOPENSSL=y
|
||||
BR2_PACKAGE_HAS_OPENSSL=y
|
||||
BR2_PACKAGE_PROVIDES_OPENSSL="libopenssl"
|
||||
BR2_PACKAGE_LIBFUSE=y
|
||||
BR2_PACKAGE_LIBFFI=y
|
||||
BR2_PACKAGE_LIBGLIB2=y
|
||||
BR2_PACKAGE_PCRE=y
|
||||
BR2_PACKAGE_PCRE_UTF=y
|
||||
BR2_PACKAGE_PCRE_UCP=y
|
||||
BR2_PACKAGE_OPENSSH=y
|
||||
BR2_PACKAGE_HOST_MKPASSWD=y
|
||||
|
||||
@ -0,0 +1,263 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import argparse
|
||||
import os
|
||||
|
||||
from litex.soc.integration.builder import Builder
|
||||
|
||||
from soc_linux import SoCLinux
|
||||
|
||||
kB = 1024
|
||||
|
||||
# Board definition----------------------------------------------------------------------------------
|
||||
|
||||
class Board:
|
||||
def __init__(self, soc_cls, soc_capabilities):
|
||||
self.soc_cls = soc_cls
|
||||
self.soc_capabilities = soc_capabilities
|
||||
|
||||
def load(self):
|
||||
raise NotImplementedError
|
||||
|
||||
def flash(self):
|
||||
raise NotImplementedError
|
||||
|
||||
# Arty support -------------------------------------------------------------------------------------
|
||||
|
||||
class Arty(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import arty
|
||||
Board.__init__(self, arty.EthernetSoC, {"serial", "ethernet", "spiflash", "leds", "switches", "spi", "i2c", "xadc"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_xilinx.cfg")
|
||||
prog.load_bitstream("build/arty/gateware/top.bit")
|
||||
|
||||
def flash(self):
|
||||
flash_regions = {
|
||||
"build/arty/gateware/top.bin": "0x00000000", # FPGA image: loaded at startup
|
||||
"buildroot/Image": "0x00400000", # Linux Image: copied to 0xc0000000 by bios
|
||||
"buildroot/rootfs.cpio": "0x00800000", # File System: copied to 0xc0800000 by bios
|
||||
"buildroot/rv32.dtb": "0x00f00000", # Device tree: copied to 0xc1000000 by bios
|
||||
"emulator/emulator.bin": "0x00f80000", # MM Emulator: copied to 0x20000000 by bios
|
||||
}
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_xilinx.cfg",
|
||||
flash_proxy_basename="prog/bscan_spi_xc7a35t.bit")
|
||||
prog.set_flash_proxy_dir(".")
|
||||
for filename, base in flash_regions.items():
|
||||
base = int(base, 16)
|
||||
print("Flashing {} at 0x{:08x}".format(filename, base))
|
||||
prog.flash(base, filename)
|
||||
|
||||
# NeTV2 support ------------------------------------------------------------------------------------
|
||||
|
||||
class NeTV2(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import netv2
|
||||
Board.__init__(self, netv2.EthernetSoC, {"serial", "ethernet", "framebuffer", "spiflash", "leds", "xadc"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.openocd import OpenOCD
|
||||
prog = OpenOCD("prog/openocd_netv2_rpi.cfg")
|
||||
prog.load_bitstream("build/netv2/gateware/top.bit")
|
||||
|
||||
# Genesys2 support ---------------------------------------------------------------------------------
|
||||
|
||||
class Genesys2(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import genesys2
|
||||
Board.__init__(self, genesys2.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/genesys2/gateware/top.bit")
|
||||
|
||||
# KCU105 support -----------------------------------------------------------------------------------
|
||||
|
||||
class KCU105(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import kcu105
|
||||
Board.__init__(self, kcu105.EthernetSoC, {"serial", "ethernet"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/kcu105/gateware/top.bit")
|
||||
|
||||
|
||||
# Nexys4DDR support --------------------------------------------------------------------------------
|
||||
|
||||
class Nexys4DDR(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import nexys4ddr
|
||||
Board.__init__(self, nexys4ddr.EthernetSoC, {"serial", "ethernet"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/nexys4ddr/gateware/top.bit")
|
||||
|
||||
# NexysVideo support --------------------------------------------------------------------------------
|
||||
|
||||
class NexysVideo(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import nexys_video
|
||||
Board.__init__(self, nexys_video.EthernetSoC, {"serial", "framebuffer"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.xilinx import VivadoProgrammer
|
||||
prog = VivadoProgrammer()
|
||||
prog.load_bitstream("build/nexys_video/gateware/top.bit")
|
||||
|
||||
# MiniSpartan6 support -----------------------------------------------------------------------------
|
||||
|
||||
class MiniSpartan6(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import minispartan6
|
||||
Board.__init__(self, minispartan6.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
os.system("xc3sprog -c ftdi build/minispartan6/gateware/top.bit")
|
||||
|
||||
|
||||
# Versa ECP5 support -------------------------------------------------------------------------------
|
||||
|
||||
class VersaECP5(Board):
|
||||
SPIFLASH_PAGE_SIZE = 256
|
||||
SPIFLASH_SECTOR_SIZE = 64*kB
|
||||
def __init__(self):
|
||||
from litex_boards.targets import versa_ecp5
|
||||
Board.__init__(self, versa_ecp5.EthernetSoC, {"serial", "ethernet", "spiflash"})
|
||||
|
||||
def load(self):
|
||||
os.system("openocd -f prog/ecp5-versa5g.cfg -c \"transport select jtag; init; svf build/versa_ecp5/gateware/top.svf; exit\"")
|
||||
|
||||
# ULX3S support ------------------------------------------------------------------------------------
|
||||
|
||||
class ULX3S(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import ulx3s
|
||||
Board.__init__(self, ulx3s.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
os.system("ujprog build/ulx3s/gateware/top.svf")
|
||||
|
||||
# TrellisBoard support ------------------------------------------------------------------------------------
|
||||
|
||||
class Trellis(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import trellisboard
|
||||
Board.__init__(self, trellisboard.EthernetSoC, "serial+ethernet")
|
||||
|
||||
def load(self):
|
||||
os.system("openocd -f prog/trellisboard.cfg -c \"transport select jtag; init; svf build/trellisboard/gateware/top.svf; exit\"")
|
||||
|
||||
# De0Nano support ------------------------------------------------------------------------------------
|
||||
|
||||
class De0Nano(Board):
|
||||
def __init__(self):
|
||||
from litex_boards.targets import de0nano
|
||||
Board.__init__(self, de0nano.BaseSoC, {"serial"})
|
||||
|
||||
def load(self):
|
||||
from litex.build.altera import USBBlaster
|
||||
prog = USBBlaster()
|
||||
prog.load_bitstream("build/de0nano/gateware/top.sof")
|
||||
|
||||
# Main ---------------------------------------------------------------------------------------------
|
||||
|
||||
supported_boards = {
|
||||
# Xilinx
|
||||
"arty": Arty,
|
||||
"netv2": NeTV2,
|
||||
"genesys2": Genesys2,
|
||||
"kcu105": KCU105,
|
||||
"nexys4ddr": Nexys4DDR,
|
||||
"nexys_video": NexysVideo,
|
||||
"minispartan6": MiniSpartan6,
|
||||
# Lattice
|
||||
"versa_ecp5": VersaECP5,
|
||||
"ulx3s": ULX3S,
|
||||
"trellisboard": Trellis,
|
||||
# Altera/Intel
|
||||
"de0nano": De0Nano,
|
||||
}
|
||||
|
||||
def main():
|
||||
description = "Linux on LiteX-VexRiscv\n\n"
|
||||
description += "Available boards:\n"
|
||||
for name in supported_boards.keys():
|
||||
description += "- " + name + "\n"
|
||||
parser = argparse.ArgumentParser(description=description, formatter_class=argparse.RawTextHelpFormatter)
|
||||
parser.add_argument("--board", required=True, help="FPGA board")
|
||||
parser.add_argument("--build", action="store_true", help="build bitstream")
|
||||
parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)")
|
||||
parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)")
|
||||
parser.add_argument("--local-ip", default="192.168.1.50", help="local IP address")
|
||||
parser.add_argument("--remote-ip", default="192.168.1.100", help="remote IP address of TFTP server")
|
||||
parser.add_argument("--spi-bpw", type=int, default=8, help="Bits per word for SPI controller")
|
||||
parser.add_argument("--spi-sck-freq", type=int, default=1e6, help="SPI clock frequency")
|
||||
args = parser.parse_args()
|
||||
|
||||
if args.board == "all":
|
||||
board_names = list(supported_boards.keys())
|
||||
else:
|
||||
board_names = [args.board]
|
||||
for board_name in board_names:
|
||||
board = supported_boards[board_name]()
|
||||
soc_kwargs = {}
|
||||
if board_name in ["versa_ecp5", "ulx3s", "trellisboard"]:
|
||||
soc_kwargs["toolchain"] = "trellis"
|
||||
soc_kwargs["cpu_variant"] = "linux+no-dsp"
|
||||
if board_name in ["de0nano"]:
|
||||
soc_kwargs["l2_size"] = 1024 # FIXME: Reduce l2_size, blockram not infered correctly?
|
||||
soc = SoCLinux(board.soc_cls, **soc_kwargs)
|
||||
if "spiflash" in board.soc_capabilities:
|
||||
soc.add_spi_flash()
|
||||
soc.add_constant("SPIFLASH_PAGE_SIZE", board.SPIFLASH_PAGE_SIZE)
|
||||
soc.add_constant("SPIFLASH_SECTOR_SIZE", board.SPIFLASH_SECTOR_SIZE)
|
||||
if "ethernet" in board.soc_capabilities:
|
||||
soc.configure_ethernet(local_ip=args.local_ip, remote_ip=args.remote_ip)
|
||||
if "leds" in board.soc_capabilities:
|
||||
soc.add_leds()
|
||||
if "switches" in board.soc_capabilities:
|
||||
soc.add_switches()
|
||||
if "spi" in board.soc_capabilities:
|
||||
soc.add_spi(args.spi_bpw, args.spi_sck_freq)
|
||||
if "i2c" in board.soc_capabilities:
|
||||
soc.add_i2c()
|
||||
if "xadc" in board.soc_capabilities:
|
||||
soc.add_xadc()
|
||||
if "framebuffer" in board.soc_capabilities:
|
||||
soc.add_framebuffer()
|
||||
soc.configure_boot()
|
||||
|
||||
build_dir = os.path.join("build", board_name)
|
||||
if args.build:
|
||||
builder = Builder(soc, output_dir=build_dir,
|
||||
csr_json=os.path.join(build_dir, "csr.json"))
|
||||
else:
|
||||
builder = Builder(soc, output_dir="build/" + board_name,
|
||||
compile_software=False, compile_gateware=False,
|
||||
csr_json=os.path.join(build_dir, "csr.json"))
|
||||
builder.build()
|
||||
|
||||
soc.generate_dts(board_name)
|
||||
soc.compile_dts(board_name)
|
||||
soc.compile_emulator(board_name)
|
||||
|
||||
if args.load:
|
||||
board.load()
|
||||
|
||||
if args.flash:
|
||||
board.flash()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@ -0,0 +1,6 @@
|
||||
Linux on LiteX-Vexriscv
|
||||
|
||||
32-bit VexRiscv CPU with MMU integrated in a LiteX SoC
|
||||
|
||||
Fork Sand Build on Trellisboard
|
||||
|
||||
@ -0,0 +1,16 @@
|
||||
auto lo
|
||||
iface lo inet loopback
|
||||
|
||||
# The primary network interface
|
||||
auto eth0 eth0:0
|
||||
iface eth0 inet static
|
||||
address 192.168.110.26
|
||||
netmask 255.255.255.0
|
||||
gateway 192.168.110.252
|
||||
dns-nameservers 192.168.110.252
|
||||
dns-search forksand.com
|
||||
|
||||
iface eth0:0 inet static
|
||||
address 192.168.1.50
|
||||
netmask 255.255.255.0
|
||||
|
||||
@ -0,0 +1,20 @@
|
||||
export PATH="/bin:/sbin:/usr/bin:/usr/sbin"
|
||||
|
||||
if [ "$PS1" ]; then
|
||||
if [ "`id -u`" -eq 0 ]; then
|
||||
export PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\# '
|
||||
else
|
||||
export PS1='\[\033[01;32m\]\u@\h\[\033[00m\]:\[\033[01;34m\]\w\[\033[00m\]\$ '
|
||||
fi
|
||||
fi
|
||||
|
||||
export PAGER='/bin/more'
|
||||
export EDITOR='/bin/vi'
|
||||
|
||||
# Source configuration files from /etc/profile.d
|
||||
for i in /etc/profile.d/*.sh ; do
|
||||
if [ -r "$i" ]; then
|
||||
. $i
|
||||
fi
|
||||
done
|
||||
unset i
|
||||
@ -0,0 +1,2 @@
|
||||
nameserver 192.168.110.252
|
||||
search forksand.com
|
||||
@ -0,0 +1,2 @@
|
||||
ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAILpztQNKt5cp2+md/Co+6bXBv56NBQvv9GQjBF73H7NG jebba@sparkle
|
||||
ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAINc+UB6SSDDm6AS3LSVyKVCtazrKDYZyTnDR2niCbojq jebba@fshq
|
||||
@ -0,0 +1,8 @@
|
||||
#!/bin/sh
|
||||
|
||||
nbd-client 192.168.110.63 8992 /dev/nbd0
|
||||
|
||||
fsck /dev/nbd0
|
||||
|
||||
mount /dev/nbd0 /mnt/
|
||||
|
||||
@ -0,0 +1,48 @@
|
||||
# this supports ulx3s
|
||||
|
||||
interface ft232r
|
||||
#ft232r_device_desc "ulx3s"
|
||||
ft232r_vid_pid 0x0403 0x6015
|
||||
# ULX3S specific GPIO setting
|
||||
ft232r_tck_num DSR
|
||||
ft232r_tms_num DCD
|
||||
ft232r_tdi_num RI
|
||||
ft232r_tdo_num CTS
|
||||
# trst/srst are not used but must have different values than above
|
||||
ft232r_trst_num RTS
|
||||
ft232r_srst_num DTR
|
||||
# default speed
|
||||
adapter_khz 1000
|
||||
|
||||
# JTAG TAPs - lfe5u12, lfe5u25, lfe5u45, lfe5u85
|
||||
#jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
|
||||
|
||||
#
|
||||
jtag newtap lfe5um85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#Error: tdo check error at line 51
|
||||
#Error: READ = 0x1113043
|
||||
#Error: WANT = 0x41113043
|
||||
#Error: MASK = 0xffffffff
|
||||
#Error: fail to run command at line 12527
|
||||
#Error: tdo check error at line 51
|
||||
#Error: READ = 0x1113043
|
||||
#Error: WANT = 0x41113043
|
||||
#Error: MASK = 0xffffffff
|
||||
|
||||
|
||||
|
||||
#
|
||||
#jtag newtap lfe5um85 tap -expected-id 0x1113043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#Error: tdo check error at line 51
|
||||
#Error: READ = 0x1113043
|
||||
#Error: WANT = 0x41113043
|
||||
#Error: MASK = 0xffffffff
|
||||
#Error: fail to run command at line 12527
|
||||
#Error: tdo check error at line 51
|
||||
#Error: READ = 0x1113043
|
||||
#Error: WANT = 0x41113043
|
||||
#Error: MASK = 0xffffffff
|
||||
|
||||
@ -0,0 +1,21 @@
|
||||
# this supports ulx3s
|
||||
|
||||
interface ft232r
|
||||
#ft232r_device_desc "ulx3s"
|
||||
ft232r_vid_pid 0x0403 0x6015
|
||||
# ULX3S specific GPIO setting
|
||||
ft232r_tck_num DSR
|
||||
ft232r_tms_num DCD
|
||||
ft232r_tdi_num RI
|
||||
ft232r_tdo_num CTS
|
||||
# trst/srst are not used but must have different values than above
|
||||
ft232r_trst_num RTS
|
||||
ft232r_srst_num DTR
|
||||
# default speed
|
||||
adapter_khz 1000
|
||||
|
||||
# JTAG TAPs - lfe5u12, lfe5u25, lfe5u45, lfe5u85
|
||||
#jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
@ -0,0 +1,21 @@
|
||||
# this supports ulx3s
|
||||
|
||||
interface ft232r
|
||||
#ft232r_device_desc "ulx3s"
|
||||
ft232r_vid_pid 0x0403 0x6015
|
||||
# ULX3S specific GPIO setting
|
||||
ft232r_tck_num DSR
|
||||
ft232r_tms_num DCD
|
||||
ft232r_tdi_num RI
|
||||
ft232r_tdo_num CTS
|
||||
# trst/srst are not used but must have different values than above
|
||||
ft232r_trst_num RTS
|
||||
ft232r_srst_num DTR
|
||||
# default speed
|
||||
adapter_khz 1000
|
||||
|
||||
# JTAG TAPs - lfe5u12, lfe5u25, lfe5u45, lfe5u85
|
||||
#jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
jtag newtap lfe5um85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
||||
@ -0,0 +1,462 @@
|
||||
BLOCK RESETPATHS;
|
||||
BLOCK ASYNCPATHS;
|
||||
## ULX3S v2.x.x and v3.0.x
|
||||
|
||||
# The clock "usb" and "gpdi" sheet
|
||||
LOCATE COMP "clk_25mhz" SITE "G2";
|
||||
IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
||||
FREQUENCY PORT "clk_25mhz" 25 MHZ;
|
||||
|
||||
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
|
||||
# write to FLASH possible any time from JTAG:
|
||||
#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
|
||||
# write to FLASH possible from user bitstream:
|
||||
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
|
||||
|
||||
## USBSERIAL FTDI-FPGA serial port "usb" sheet
|
||||
LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi
|
||||
LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi
|
||||
LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives
|
||||
LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives
|
||||
LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives
|
||||
IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
|
||||
## LED indicators "blinkey" and "gpio" sheet
|
||||
LOCATE COMP "led[7]" SITE "H3";
|
||||
LOCATE COMP "led[6]" SITE "E1";
|
||||
LOCATE COMP "led[5]" SITE "E2";
|
||||
LOCATE COMP "led[4]" SITE "D1";
|
||||
LOCATE COMP "led[3]" SITE "D2";
|
||||
LOCATE COMP "led[2]" SITE "C1";
|
||||
LOCATE COMP "led[1]" SITE "C2";
|
||||
LOCATE COMP "led[0]" SITE "B2";
|
||||
IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet
|
||||
LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic)
|
||||
LOCATE COMP "btn[1]" SITE "R1"; # FIRE1
|
||||
LOCATE COMP "btn[2]" SITE "T1"; # FIRE2
|
||||
LOCATE COMP "btn[3]" SITE "R18"; # UP
|
||||
LOCATE COMP "btn[4]" SITE "V1"; # DOWN
|
||||
LOCATE COMP "btn[5]" SITE "U1"; # LEFT
|
||||
LOCATE COMP "btn[6]" SITE "H16"; # RIGHT
|
||||
IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
|
||||
## DIP switch "blinkey", "gpio" sheet
|
||||
LOCATE COMP "sw[0]" SITE "E8"; # SW1
|
||||
LOCATE COMP "sw[1]" SITE "D8"; # SW2
|
||||
LOCATE COMP "sw[2]" SITE "D7"; # SW3
|
||||
LOCATE COMP "sw[3]" SITE "E7"; # SW4
|
||||
IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33;
|
||||
|
||||
## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet
|
||||
LOCATE COMP "oled_clk" SITE "P4";
|
||||
LOCATE COMP "oled_mosi" SITE "P3";
|
||||
LOCATE COMP "oled_dc" SITE "P1";
|
||||
LOCATE COMP "oled_resn" SITE "P2";
|
||||
LOCATE COMP "oled_csn" SITE "N2";
|
||||
IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SPI Flash chip "flash" sheet
|
||||
LOCATE COMP "flash_csn" SITE "R2";
|
||||
#LOCATE COMP "flash_clk" SITE "U3";
|
||||
LOCATE COMP "flash_mosi" SITE "W2";
|
||||
LOCATE COMP "flash_miso" SITE "V2";
|
||||
LOCATE COMP "flash_holdn" SITE "W1";
|
||||
LOCATE COMP "flash_wpn" SITE "Y2";
|
||||
#LOCATE COMP "flash_csspin" SITE "AJ3";
|
||||
#LOCATE COMP "flash_initn" SITE "AG4";
|
||||
#LOCATE COMP "flash_done" SITE "AJ4";
|
||||
#LOCATE COMP "flash_programn" SITE "AH4";
|
||||
#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
|
||||
#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
|
||||
#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
|
||||
IOBUF PORT "flash_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_mosi" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_miso" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_holdn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_wpn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SD card "sdcard", "usb" sheet
|
||||
LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14
|
||||
LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
|
||||
LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2
|
||||
LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4
|
||||
LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12
|
||||
LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13
|
||||
LOCATE COMP "sd_wp" SITE "P5"; # not connected
|
||||
LOCATE COMP "sd_cdn" SITE "N5"; # not connected
|
||||
IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement
|
||||
IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## ADC SPI (MAX11123) "analog", "ram" sheet
|
||||
LOCATE COMP "adc_csn" SITE "R17";
|
||||
LOCATE COMP "adc_mosi" SITE "R16";
|
||||
LOCATE COMP "adc_miso" SITE "U16";
|
||||
LOCATE COMP "adc_sclk" SITE "P17";
|
||||
IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Audio 4-bit DAC "analog", "gpio" sheet
|
||||
# Output impedance 75 ohm.
|
||||
# Strong enough to drive 16 ohm earphones.
|
||||
LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio)
|
||||
LOCATE COMP "audio_l[2]" SITE "C3";
|
||||
LOCATE COMP "audio_l[1]" SITE "D3";
|
||||
LOCATE COMP "audio_l[0]" SITE "E4";
|
||||
LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio)
|
||||
LOCATE COMP "audio_r[2]" SITE "D5";
|
||||
LOCATE COMP "audio_r[1]" SITE "B5";
|
||||
LOCATE COMP "audio_r[0]" SITE "A3";
|
||||
LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio)
|
||||
LOCATE COMP "audio_v[2]" SITE "F5";
|
||||
LOCATE COMP "audio_v[1]" SITE "F2";
|
||||
LOCATE COMP "audio_v[0]" SITE "H5";
|
||||
IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
|
||||
## WiFi ESP-32 "wifi", "usb", "flash" sheet
|
||||
# other pins are shared with GP/GN, SD card and JTAG
|
||||
LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi
|
||||
LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi
|
||||
LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi
|
||||
LOCATE COMP "wifi_gpio0" SITE "L2";
|
||||
LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED
|
||||
LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX
|
||||
LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX
|
||||
# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active
|
||||
IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## PCB antenna 433 MHz (may be also used for FM) "usb" sheet
|
||||
LOCATE COMP "ant_433mhz" SITE "G1";
|
||||
IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
|
||||
LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only
|
||||
LOCATE COMP "usb_fpga_dn" SITE "F16";
|
||||
IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
||||
IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
||||
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional
|
||||
LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
|
||||
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control
|
||||
LOCATE COMP "usb_fpga_pu_dn" SITE "C12";
|
||||
IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
|
||||
## JTAG ESP-32 "usb" sheet
|
||||
# connected to FT231X and ESP-32
|
||||
# commented out because those are dedicated pins, not directly useable as GPIO
|
||||
# but could be used by some vendor-specific JTAG bridging (boundary scan) module
|
||||
#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives
|
||||
#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits
|
||||
#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives
|
||||
#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives
|
||||
#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SDRAM "ram" sheet
|
||||
LOCATE COMP "sdram_clk" SITE "F19";
|
||||
LOCATE COMP "sdram_cke" SITE "F20";
|
||||
LOCATE COMP "sdram_csn" SITE "P20";
|
||||
LOCATE COMP "sdram_wen" SITE "T20";
|
||||
LOCATE COMP "sdram_rasn" SITE "R20";
|
||||
LOCATE COMP "sdram_casn" SITE "T19";
|
||||
LOCATE COMP "sdram_a[0]" SITE "M20";
|
||||
LOCATE COMP "sdram_a[1]" SITE "M19";
|
||||
LOCATE COMP "sdram_a[2]" SITE "L20";
|
||||
LOCATE COMP "sdram_a[3]" SITE "L19";
|
||||
LOCATE COMP "sdram_a[4]" SITE "K20";
|
||||
LOCATE COMP "sdram_a[5]" SITE "K19";
|
||||
LOCATE COMP "sdram_a[6]" SITE "K18";
|
||||
LOCATE COMP "sdram_a[7]" SITE "J20";
|
||||
LOCATE COMP "sdram_a[8]" SITE "J19";
|
||||
LOCATE COMP "sdram_a[9]" SITE "H20";
|
||||
LOCATE COMP "sdram_a[10]" SITE "N19";
|
||||
LOCATE COMP "sdram_a[11]" SITE "G20";
|
||||
LOCATE COMP "sdram_a[12]" SITE "G19";
|
||||
LOCATE COMP "sdram_ba[0]" SITE "P19";
|
||||
LOCATE COMP "sdram_ba[1]" SITE "N20";
|
||||
LOCATE COMP "sdram_dqm[0]" SITE "U19";
|
||||
LOCATE COMP "sdram_dqm[1]" SITE "E20";
|
||||
LOCATE COMP "sdram_d[0]" SITE "J16";
|
||||
LOCATE COMP "sdram_d[1]" SITE "L18";
|
||||
LOCATE COMP "sdram_d[2]" SITE "M18";
|
||||
LOCATE COMP "sdram_d[3]" SITE "N18";
|
||||
LOCATE COMP "sdram_d[4]" SITE "P18";
|
||||
LOCATE COMP "sdram_d[5]" SITE "T18";
|
||||
LOCATE COMP "sdram_d[6]" SITE "T17";
|
||||
LOCATE COMP "sdram_d[7]" SITE "U20";
|
||||
LOCATE COMP "sdram_d[8]" SITE "E19";
|
||||
LOCATE COMP "sdram_d[9]" SITE "D20";
|
||||
LOCATE COMP "sdram_d[10]" SITE "D19";
|
||||
LOCATE COMP "sdram_d[11]" SITE "C20";
|
||||
LOCATE COMP "sdram_d[12]" SITE "E18";
|
||||
LOCATE COMP "sdram_d[13]" SITE "F18";
|
||||
LOCATE COMP "sdram_d[14]" SITE "J18";
|
||||
LOCATE COMP "sdram_d[15]" SITE "J17";
|
||||
IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
# GPDI differential interface (Video) "gpdi" sheet
|
||||
LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue +
|
||||
LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue -
|
||||
LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green +
|
||||
LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green -
|
||||
LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red +
|
||||
LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red -
|
||||
LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock +
|
||||
LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock -
|
||||
LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet +
|
||||
LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
|
||||
LOCATE COMP "gpdi_cec" SITE "A18";
|
||||
LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
|
||||
LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
|
||||
IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
|
||||
# Physical connector pins:
|
||||
# *** when FEMALE ANGLED (90 deg PMOD) soldered ***
|
||||
# Jm_n- = Jm_n, Jm_n+ = Jm_n+1
|
||||
# example: J1_5- is J1_5 phsyical, J1_5+ is J1_6 physical
|
||||
# *** when MALE VERTICAL soldered ***
|
||||
# Jm_n+ = Jm_n, Jm_n- = Jm_n+1
|
||||
# example: J1_5+ is J1_5 physical, J1_5- is J1_6 physical
|
||||
# Pins enumerated gp[0-27], gn[0-27].
|
||||
# With differential mode enabled on Lattice,
|
||||
# gp[] (+) are used, gn[] (-) are ignored from design
|
||||
# as they handle inverted signal by default.
|
||||
# To enable differential, rename LVCMOS33->LVCMOS33D
|
||||
# To enable clock i/o, add this (example):
|
||||
#FREQUENCY PORT "gp[12]" 25.00 MHZ;
|
||||
LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 PCLK
|
||||
LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 PCLK
|
||||
LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 PCLK
|
||||
LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 PCLK
|
||||
LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 GR_PCLK
|
||||
LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 GR_PCLK
|
||||
LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3
|
||||
LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3
|
||||
LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4
|
||||
LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4
|
||||
LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5
|
||||
LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5
|
||||
LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6
|
||||
LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6
|
||||
IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7
|
||||
LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7
|
||||
LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8
|
||||
LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 DIFF
|
||||
LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 DIFF
|
||||
LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 DIFF
|
||||
LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 DIFF
|
||||
LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 DIFF
|
||||
LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 DIFF WIFI_GPIO26
|
||||
LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 DIFF WIFI_GPIO25
|
||||
LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 DIFF WIFI_GPIO33 PCLK
|
||||
LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 DIFF WIFI_GPIO32 PCLK
|
||||
LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 DIFF WIFI_GPIO35
|
||||
LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 DIFF WIFI_GPIO34
|
||||
IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 DIFF ADC1
|
||||
LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 DIFF ADC0
|
||||
LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 DIFF ADC3
|
||||
LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 DIFF ADC2
|
||||
LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 DIFF ADC5
|
||||
LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 DIFF ADC4
|
||||
LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 DIFF ADC7 GR_PCLK
|
||||
LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 DIFF ADC6
|
||||
LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 DIFF
|
||||
LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 DIFF
|
||||
LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 DIFF
|
||||
LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 DIFF
|
||||
LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 DIFF
|
||||
LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 DIFF
|
||||
IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 DIFF
|
||||
LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 DIFF
|
||||
LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22
|
||||
LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22
|
||||
LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23
|
||||
LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23
|
||||
LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24
|
||||
LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24
|
||||
LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25
|
||||
LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25
|
||||
LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26
|
||||
LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26
|
||||
LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27
|
||||
LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27
|
||||
IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
|
||||
# PCB v2.0.5 and higher
|
||||
LOCATE COMP "user_programn" SITE "M4";
|
||||
IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
|
||||
# on PCB v1.7 shutdown is not connected to FPGA
|
||||
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
|
||||
IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
@ -1,3 +1,8 @@
|
||||
# fpga-cruft
|
||||
|
||||
Crufty scripts.
|
||||
Crufty scripts for FPGAs.
|
||||
|
||||
WARNING: these scripts aren't set up for general use.
|
||||
|
||||
Read the scripts before running, they may do who-knows-what.
|
||||
|
||||
|
||||
@ -0,0 +1,16 @@
|
||||
# this supports ECP5 Evaluation Board
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Lattice ECP5 Evaluation Board"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
# channel 1 does not have any functionality
|
||||
ftdi_channel 0
|
||||
# just TCK TDI TDO TMS, no reset
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
|
||||
# default speed
|
||||
adapter_khz 5000
|
||||
|
||||
# ECP5 device - LFE5UM5G-85F
|
||||
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
|
||||
@ -0,0 +1,18 @@
|
||||
# this supports ECP5 Versa board
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Lattice ECP5 Versa Board"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
# channel 1 does not have any functionality
|
||||
ftdi_channel 0
|
||||
# just TCK TDI TDO TMS, no reset
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
|
||||
# default speed
|
||||
adapter_khz 25000
|
||||
|
||||
# ispCLOCK device (should be bypassed by jumpers as it causes problems)
|
||||
#jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
|
||||
# ECP5 device - LFE5UM-45F
|
||||
jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043
|
||||
@ -0,0 +1,18 @@
|
||||
# this supports ECP5 Versa board
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Lattice ECP5_5G VERSA Board"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
# channel 1 does not have any functionality
|
||||
ftdi_channel 0
|
||||
# just TCK TDI TDO TMS, no reset
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
|
||||
# default speed
|
||||
adapter_khz 25000
|
||||
|
||||
# ispCLOCK device (should be bypassed by jumpers as it causes problems)
|
||||
#jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
|
||||
# ECP5 device - LFE5UM5G-45F
|
||||
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
|
||||
@ -0,0 +1,18 @@
|
||||
# this supports ECP5 Versa board
|
||||
|
||||
interface ftdi
|
||||
ftdi_device_desc "Lattice ECP5_5G VERSA Board"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
# channel 1 does not have any functionality
|
||||
ftdi_channel 0
|
||||
# just TCK TDI TDO TMS, no reset
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
|
||||
# default speed
|
||||
adapter_khz 25000
|
||||
|
||||
# ispCLOCK device (should be bypassed by jumpers as it causes problems)
|
||||
#jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
|
||||
# ECP5 device - LFE5UM5G-45F
|
||||
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
|
||||
@ -0,0 +1,16 @@
|
||||
# TrellisBoard OpenOCD config
|
||||
|
||||
interface ftdi
|
||||
# ftdi_device_desc "TrellisBoard"
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
# channel 1 does not have any functionality
|
||||
ftdi_channel 0
|
||||
# just TCK TDI TDO TMS, no reset
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
reset_config none
|
||||
|
||||
# default speed
|
||||
adapter_khz 5000
|
||||
|
||||
# ECP5 device - LFE5UM5G-85F
|
||||
jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
|
||||
@ -0,0 +1,15 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
for i in /dev/ttyUSB1
|
||||
do echo "USB Devices to use: $i"
|
||||
done
|
||||
|
||||
for i in /dev/ttyUSB1
|
||||
do echo "Using: $i"
|
||||
lxterm --images=images.json $i --speed=2e6 --no-crc
|
||||
done
|
||||
|
||||
|
||||
#--serial-boot
|
||||
@ -0,0 +1,5 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
openocd -f ./ecp5.cfg -c "transport select jtag; init; svf ./SVF.svf; exit"
|
||||
@ -0,0 +1,13 @@
|
||||
#!/bin/bash
|
||||
|
||||
cd ~/devel/FPGA
|
||||
|
||||
for i in `find . -name .git | sort`
|
||||
do echo
|
||||
cd ~/devel/FPGA
|
||||
echo $i | sed -e 's/\.git$//g' | sed -e 's/^\.\///g'
|
||||
cd `dirname $i`
|
||||
git branch
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
done
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
#!/bin/bash
|
||||
|
||||
NOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
./forksand-fpga-git-commits > git-commit-versions/$NOW 2> git-commit-versions/$NOW-err
|
||||
|
||||
@ -0,0 +1,11 @@
|
||||
#!/bin/bash
|
||||
|
||||
#lxterm --images=jeboot.json /dev/ttyUSB1 --speed=2e6 --no-crc
|
||||
#--serial-boot
|
||||
|
||||
openocd -f ./ecp5.cfg -c "transport select jtag; init; svf ./SVF.svf; exit"
|
||||
|
||||
echo "Now run:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "or"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
@ -0,0 +1,11 @@
|
||||
#!/bin/bash
|
||||
|
||||
cd /home/jebba/devel/FPGA/litex/linux-on-litex-vexriscv
|
||||
|
||||
#./make.py --board versa_ecp5 --build
|
||||
./make.py --board versa_ecp5 --load
|
||||
#./make.py --board versa_ecp5 --flash
|
||||
|
||||
echo "Now run this to get the console"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
# Wt
|
||||
cd /home/jebba/devel/FPGA/litex/litex/litex/boards/targets
|
||||
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_ethernetsoc_versa_ecp5
|
||||
|
||||
echo
|
||||
echo "NOW BUILDING"
|
||||
echo
|
||||
|
||||
# Build .svf
|
||||
./versa_ecp5.py \
|
||||
--sys-clk-freq=66666666 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--cpu-variant=linux+no-dsp \
|
||||
--csr-csv=./csr_ecp5versa.csv \
|
||||
|| exit
|
||||
|
||||
# If you add/remove ethernet, also need to change .svf below
|
||||
# --with-ethernet \
|
||||
# --cpu-variant=linux \
|
||||
# --cpu-variant=linux+no-dsp \
|
||||
# --cpu-type=rocket \
|
||||
# --sys-clk-freq=60e6 \
|
||||
|
||||
|
||||
echo
|
||||
echo "NOW FLASHING"
|
||||
echo
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/ecp5-versa5g.cfg \
|
||||
-c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|| exit
|
||||
# No ethernet
|
||||
# XXX UPDATE
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
# With ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|
||||
|
||||
echo "Running:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "Hit ctrl-c twice to bail"
|
||||
echo
|
||||
echo "If that lxterm doesn't connect try like this:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
echo
|
||||
echo "NOW CONNECTING"
|
||||
echo
|
||||
|
||||
#lxterm /dev/ttyUSB1
|
||||
|
||||
echo "no, really gonna try to load a kernel instead:"
|
||||
echo "lxterm --images=/home/jebba/devel/FPGA/muh/jeboot.json /dev/ttyUSB1 --no-crc --speed=1e6"
|
||||
|
||||
@ -0,0 +1,60 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
# Wt
|
||||
cd /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets
|
||||
|
||||
rm -fr /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/
|
||||
|
||||
echo
|
||||
echo "NOW BUILDING"
|
||||
echo
|
||||
|
||||
# Build .svf
|
||||
./versa_ecp5.py \
|
||||
--sys-clk-freq=60e6 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--csr-csv=./csr_ecp5versa.csv \
|
||||
|| exit
|
||||
|
||||
# If you add/remove ethernet, also need to change .svf below
|
||||
# --cpu-type=rocket
|
||||
# --sys-clk-freq=60e6 \
|
||||
# --with-ethernet \
|
||||
# --cpu-variant=linux \
|
||||
|
||||
|
||||
exit 0
|
||||
|
||||
echo
|
||||
echo "NOW FLASHING"
|
||||
echo
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/ecp5-versa5g.cfg \
|
||||
-c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|| exit
|
||||
# No ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
# With ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|
||||
|
||||
|
||||
|
||||
echo "Running:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "Hit ctrl-c twice to bail"
|
||||
echo
|
||||
echo "If that lxterm doesn't connect try like this:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
echo
|
||||
echo "NOW CONNECTING"
|
||||
echo
|
||||
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
@ -0,0 +1,56 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
# Wt
|
||||
cd /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets
|
||||
#rm -f /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf
|
||||
rm -fr /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/
|
||||
|
||||
echo
|
||||
echo "NOW BUILDING"
|
||||
echo
|
||||
|
||||
# Build .svf
|
||||
./versa_ecp5.py \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--csr-csv=./csr_ecp5versa.csv \
|
||||
|| exit
|
||||
|
||||
# --cpu-type=rocket
|
||||
# --sys-clk-freq=60e6 \
|
||||
# --with-ethernet \
|
||||
# --cpu-variant=linux \
|
||||
|
||||
|
||||
echo
|
||||
echo "NOW FLASHING"
|
||||
echo
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/ecp5-versa5g.cfg \
|
||||
-c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|| exit
|
||||
# No ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
# With ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|
||||
|
||||
|
||||
|
||||
echo "Running:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "Hit ctrl-c twice to bail"
|
||||
echo
|
||||
echo "If that lxterm doesn't connect try like this:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
echo
|
||||
echo "NOW CONNECTING"
|
||||
echo
|
||||
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
@ -0,0 +1,57 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
# Wt
|
||||
cd /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets
|
||||
#rm -f /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf
|
||||
rm -fr /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/
|
||||
|
||||
echo
|
||||
echo "NOW BUILDING"
|
||||
echo
|
||||
|
||||
# Build .svf
|
||||
./versa_ecp5.py \
|
||||
--sys-clk-freq=60e6 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--csr-csv=./csr_ecp5versa.csv \
|
||||
|| exit
|
||||
|
||||
# --cpu-type=rocket
|
||||
# --sys-clk-freq=60e6 \
|
||||
# --with-ethernet \
|
||||
# --cpu-variant=linux \
|
||||
|
||||
|
||||
echo
|
||||
echo "NOW FLASHING"
|
||||
echo
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/ecp5-versa5g.cfg \
|
||||
-c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|| exit
|
||||
# No ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
# With ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|
||||
|
||||
|
||||
|
||||
echo "Running:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "Hit ctrl-c twice to bail"
|
||||
echo
|
||||
echo "If that lxterm doesn't connect try like this:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
echo
|
||||
echo "NOW CONNECTING"
|
||||
echo
|
||||
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
@ -0,0 +1,17 @@
|
||||
#/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
cd ~/devel/FPGA/litex/litex/litex/boards/targets
|
||||
|
||||
./versa_ecp5.py
|
||||
--gateware-toolchain trellis
|
||||
--csr-csv ./csr_ecp5versa.csv
|
||||
--with-ethernet
|
||||
--sys-clk-freq=60e6
|
||||
--cpu-type vexriscv
|
||||
--cpu-variant linux
|
||||
|
||||
exit 0
|
||||
|
||||
--cpu-type rocket
|
||||
@ -0,0 +1,8 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
for i in /dev/ttyUSB1
|
||||
do echo $i
|
||||
lxterm $i
|
||||
done
|
||||
@ -0,0 +1,7 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
#xterm /dev/USB1 --speed=2e6
|
||||
xterm /dev/USB1 --speed=1e6
|
||||
|
||||
@ -0,0 +1,495 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# This updates every repo, rebuilds everything.
|
||||
# Creates:
|
||||
# RISC-V 32-bit core running Linux with root filesystem for ECP5 FPGA.
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-$FPGANOW) 2>>$FPGADIR/log/trellis-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGASCRIPTS || exit
|
||||
|
||||
# Write log of current git commits
|
||||
./forksand-fpga-git-commits-log
|
||||
|
||||
###################################
|
||||
# Update and build icestorm tools #
|
||||
###################################
|
||||
cd $FPGADIR || exit
|
||||
|
||||
# Update Icestorm
|
||||
echo "===================================== Update icestorm"
|
||||
cd icestorm && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " " && \
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
# 18 seconds:
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
# Update Pjtrellis
|
||||
echo "===================================== Update pjtrellis"
|
||||
cd prjtrellis && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
cd libtrellis && \
|
||||
make clean && \
|
||||
cmake -DCMAKE_INSTALL_PREFIX=/usr/local . && \
|
||||
# 1 second:
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ../..
|
||||
|
||||
# Update Nextpnr
|
||||
echo "===================================== Update nextpnr"
|
||||
cd nextpnr && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
cmake -DARCH=ecp5 -DCMAKE_INSTALL_PREFIX=/usr/local . && \
|
||||
# 4m40s:
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
# Update Yosys
|
||||
echo "===================================== Update yosys"
|
||||
cd yosys && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
YOABCREV=`grep ^ABCREV Makefile |cut -f 2 -d "=" | sed -e 's/ //g'` && \
|
||||
cd abc && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
git checkout $YOABCREV && \
|
||||
# 4 seconds:
|
||||
# XXX which file XXX
|
||||
#make -j$(nproc) && \
|
||||
cd ..
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
# Update OpenOCD
|
||||
echo "===================================== Update openocd"
|
||||
cd openocd && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
# 13 seconds:
|
||||
make && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
###############
|
||||
# Build LiteX #
|
||||
###############
|
||||
cd $FPGADIR/litex
|
||||
|
||||
# Update Buildroot
|
||||
echo "===================================== Update buildroot"
|
||||
cd buildroot && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
# XXX Use custom linux.config
|
||||
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
|
||||
# XXX Set up rootfs overlay files defined here:
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
cp -a $FPGADIR/PATCH/rootfs_overlay \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
# XXX Use custom defconfig
|
||||
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
|
||||
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
|
||||
# 5m16s:
|
||||
make && \
|
||||
# XXX COPY OUTPUT
|
||||
# XXX *output/images/*
|
||||
# Since tftp server is remote, mount it locally for convenience:
|
||||
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
|
||||
cp -p output/images/Image /srv/tftp/Image && \
|
||||
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
|
||||
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
|
||||
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
|
||||
|
||||
cd ..
|
||||
|
||||
# Update migen
|
||||
echo "===================================== Update migen"
|
||||
cd migen && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litedram
|
||||
echo "===================================== Update litedram"
|
||||
cd litedram && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update liteeth
|
||||
echo "===================================== Update liteeth"
|
||||
cd liteeth && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litepcie
|
||||
echo "===================================== Update litepcie"
|
||||
cd litepcie && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litesdcard
|
||||
echo "===================================== Update litesdcard"
|
||||
cd litesdcard && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litevideo
|
||||
echo "===================================== Update litevideo"
|
||||
cd litevideo && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update liteiclink
|
||||
echo "===================================== Update liteiclink"
|
||||
# XXX needed?
|
||||
cd liteiclink && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litejesd204b
|
||||
echo "===================================== Update litejesd204b"
|
||||
# XXX needed?
|
||||
cd litejesd204b && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litesata
|
||||
echo "===================================== Update litesata"
|
||||
# XXX needed?
|
||||
cd litesata && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litex-boards
|
||||
echo "===================================== Update litex-boards"
|
||||
# XXX BUILD
|
||||
cd litex-boards && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# 1 second:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
|
||||
# Update litex
|
||||
echo "===================================== Update litex"
|
||||
# XXX BUILD
|
||||
cd litex && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# XXX need to patch:
|
||||
# XXX MEMORY PATCH AND MORE HERE
|
||||
#cp -p $FPGADIR/PATCH/litex-soc_core.py \
|
||||
# ./litex/soc/integration/soc_core.py && \
|
||||
# XXX
|
||||
# Set memory in crufty way: XXX
|
||||
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x40000000) # FIXME: limit to 1G for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
|
||||
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
|
||||
#sed -i -e 's///g' $FPGADIR/litex/litex/litex/soc/integration/soc_core.py
|
||||
# BUILD VexRiscv.v HERE XXX
|
||||
cd litex/soc/cores/cpu/vexriscv/verilog && \
|
||||
# Remove older builds
|
||||
rm -f *.v && \
|
||||
# BUILD VEXRISCV
|
||||
# 1m8s:
|
||||
make && \
|
||||
cd ../../../../../.. && \
|
||||
# Build LiteX
|
||||
# 7 seconds:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user && \
|
||||
# REVERT memory in crufty way: XXX
|
||||
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x40000000) # FIXME: limit to 1G for now/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
|
||||
#sed -i -e 's/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
|
||||
cd .. && \
|
||||
#####################
|
||||
# Build RISC-V Core #
|
||||
#####################
|
||||
# XXX This build is done in above LiteX subdir
|
||||
# XXX So this is unused duplicate
|
||||
# XXX Should this really be built here earlier???
|
||||
# $FPGADIR/litex/litex/litex/soc/cores/cpu/vexriscv/verilog
|
||||
#
|
||||
# Update Vexrisc-verilog
|
||||
echo "===================================== Update vexrisc-verilog"
|
||||
# XXX BUILD
|
||||
cd Vexriscv-verilog && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# XXX clean thusly?
|
||||
# 5 seconds:
|
||||
sbt clean reload && \
|
||||
# XXX Just checkout VexRiscv_LinuxNoDspFmax ?
|
||||
# sbt "runMain vexriscv.GenCoreDefault"
|
||||
# 10 seconds:
|
||||
sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal" && \
|
||||
# XXX OUTPUT FILES:
|
||||
# VexRiscv.v VexRiscv.yaml
|
||||
cd ..
|
||||
|
||||
########################
|
||||
# Build Linux on LiteX #
|
||||
########################
|
||||
|
||||
# Update Linux on LiteX Vexriscv
|
||||
echo "===================================== Update linux-on-litex-vexriscv"
|
||||
# XXX BUILD
|
||||
cd linux-on-litex-vexriscv && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
# Clean
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/__pycache__/ && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/build && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/rv32.dtb && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.d && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.o && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.bin && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.elf && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg && \
|
||||
# Checkout custom branch
|
||||
#git checkout fs-trellis && \
|
||||
#git status && \
|
||||
#git log | head -1 | cut -f 2 -d " "
|
||||
# XXX PATCH
|
||||
# XXX set ramdisk_size=131072
|
||||
#sed -i -e 's/root=\/dev\/ram0 init=/root=\/dev\/ram0 ramdisk_size=65536 debug init=/g' json2dts.py
|
||||
# root=nbd:<server>:<port>[:<fstype>][:<mountopts>]
|
||||
# XXX
|
||||
# sed -i -e 's/root=\/dev\/ram0 init=/root=nbd:192.168.1.100:8992 debug init=/g' json2dts.py
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
# TrellisBoard Patch to make.py
|
||||
patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff && \
|
||||
# TrellisBoard config
|
||||
cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg && \
|
||||
# motd :)
|
||||
cp -p $FPGADIR/PATCH/linux-on-litex-motd \
|
||||
buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd && \
|
||||
# motd date
|
||||
echo "motd date `date`" >> buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd
|
||||
# XXX BUILD
|
||||
# XXX Add output of Vexrisc.v and buildroot etc from above
|
||||
#
|
||||
#
|
||||
# Really need to fix:
|
||||
# 2m1s:
|
||||
# XXX It actually builds, then fails at the end on something else (?)
|
||||
# This is now broken: XXX NOW OK
|
||||
./make.py --board=trellisboard --build
|
||||
#
|
||||
# Temporary work around:
|
||||
#cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets
|
||||
#rm -rf soc_ethernetsoc_trellisboard
|
||||
#./trellisboard.py \
|
||||
# --with-ethernet \
|
||||
# --sys-clk-freq=75e6 \
|
||||
# --gateware-toolchain=trellis \
|
||||
# --gateware-toolchain-path=/usr/local \
|
||||
# --cpu-type=vexriscv \
|
||||
# --cpu-variant=linux+no-dsp \
|
||||
# --csr-csv=./csr_trellisboard.csv
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
# XXX extra cruft
|
||||
#cd ~/FPGADIR/litex/linux-on-litex-vexriscv && \
|
||||
## Now comment out the line that fails in make.py and rerun to get rest of build...
|
||||
#sed -i -e 's/builder.build()/#builder.build()/g' make.py && \
|
||||
#./make.py --board=trellisboard --build && \
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
# XXX Copy to tftp server 1 file needed ?
|
||||
cp -p buildroot/rv32.dtb /srv/tftp/rv32.dtb && \
|
||||
# XXX copy to tftp server emulator.bin
|
||||
cp -p emulator/emulator.bin /srv/tftp/emulator.bin && \
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
# Load image on FPGA
|
||||
# XXX busted:
|
||||
./make.py --board=trellisboard --load && \
|
||||
# Use this to flash since make.py broken:
|
||||
#cd $FPGADIR
|
||||
#openocd \
|
||||
# -f litex/linux-on-litex-vexriscv/prog/trellisboard.cfg \
|
||||
# -c "init; svf litex/litex-boards/litex_boards/partner/targets/soc_ethernetsoc_trellisboard/gateware/top.svf ; exit"
|
||||
## -c "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/top.svf ; exit"
|
||||
cd ..
|
||||
######################
|
||||
# Load image on FPGA #
|
||||
######################
|
||||
# Done above
|
||||
# openocd
|
||||
###################
|
||||
# Connect to FPGA #
|
||||
###################
|
||||
# lxterm
|
||||
# lxterm /dev/ttyUSB1
|
||||
# lxterm /dev/ttyUSB1 --speed=2e6
|
||||
# lxterm /dev/ttyUSB1 --speed=1e6
|
||||
echo "Connect to FPGA thusly:" && \
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
|
||||
lxterm /dev/ttyUSB1 --speed=1e6
|
||||
lxterm /dev/ttyUSB2 --speed=1e6
|
||||
########
|
||||
# MISC #
|
||||
########
|
||||
# Update GCC toolchain
|
||||
#######
|
||||
# END #
|
||||
#######
|
||||
exit 0
|
||||
@ -0,0 +1,76 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Just update buildroot
|
||||
|
||||
# config kernel
|
||||
# cd /home/jebba/devel/FPGA/litex/buildroot/output/build/linux-5.0.13
|
||||
# make ARCH=riscv CROSS_COMPILE="/home/jebba/devel/FPGA/litex/buildroot/output/host/bin/riscv32-buildroot-linux-gnu-" menuconfig
|
||||
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-buildroot-$FPGANOW) 2>>$FPGADIR/log/trellis-buildroot-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
###############
|
||||
# Build LiteX #
|
||||
###############
|
||||
cd $FPGADIR/litex
|
||||
|
||||
# Update Buildroot
|
||||
echo "===================================== Build buildroot"
|
||||
cd buildroot && \
|
||||
# XXX Use custom linux.config
|
||||
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
|
||||
# XXX Set up rootfs overlay files defined here:
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
cp -a $FPGADIR/PATCH/rootfs_overlay \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
# XXX Use custom defconfig
|
||||
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
|
||||
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
|
||||
# 5m16s:
|
||||
make && \
|
||||
# XXX COPY OUTPUT
|
||||
# XXX *output/images/*
|
||||
# Since tftp server is remote, mount it locally for convenience:
|
||||
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
|
||||
cp -p output/images/Image /srv/tftp/Image && \
|
||||
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
|
||||
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
|
||||
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
|
||||
|
||||
##################
|
||||
# Linux on LiteX #
|
||||
##################
|
||||
|
||||
cd $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
# Load image on FPGA
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
# XXX
|
||||
./make.py --board=trellisboard --load
|
||||
|
||||
###################
|
||||
# Connect to FPGA #
|
||||
###################
|
||||
# lxterm
|
||||
# lxterm /dev/ttyUSB1
|
||||
# lxterm /dev/ttyUSB1 --speed=2e6
|
||||
# lxterm /dev/ttyUSB1 --speed=1e6
|
||||
echo "Connect to FPGA thusly:" && \
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6" && \
|
||||
#lxterm /dev/ttyUSB1 --speed=1e6
|
||||
#lxterm /dev/ttyUSB2 --speed=1e6
|
||||
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,88 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Just update buildroot
|
||||
|
||||
|
||||
|
||||
# config kernel
|
||||
# cd /home/jebba/devel/FPGA/litex/buildroot/output/build/linux-5.0.13
|
||||
# make ARCH=riscv CROSS_COMPILE="/home/jebba/devel/FPGA/litex/buildroot/output/host/bin/riscv32-buildroot-linux-gnu-" menuconfig
|
||||
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-buildroot-$FPGANOW) 2>>$FPGADIR/log/trellis-buildroot-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGASCRIPTS || exit
|
||||
|
||||
###############
|
||||
# Build LiteX #
|
||||
###############
|
||||
cd $FPGADIR/litex
|
||||
|
||||
# Update Buildroot
|
||||
echo "===================================== Update buildroot"
|
||||
cd buildroot && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
git pull && \
|
||||
git submodule update && \
|
||||
make clean && \
|
||||
# XXX Use custom linux.config
|
||||
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
|
||||
# XXX Set up rootfs overlay files defined here:
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
cp -a $FPGADIR/PATCH/rootfs_overlay \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
# XXX Use custom defconfig
|
||||
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
|
||||
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
|
||||
# 5m16s:
|
||||
make && \
|
||||
# XXX COPY OUTPUT
|
||||
# XXX *output/images/*
|
||||
# Since tftp server is remote, mount it locally for convenience:
|
||||
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
|
||||
cp -p output/images/Image /srv/tftp/Image && \
|
||||
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
|
||||
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
|
||||
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
|
||||
|
||||
##################
|
||||
# Linux on LiteX #
|
||||
##################
|
||||
|
||||
cd $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
# Load image on FPGA
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
# XXX
|
||||
./make.py --board=trellisboard --load
|
||||
|
||||
###################
|
||||
# Connect to FPGA #
|
||||
###################
|
||||
# lxterm
|
||||
# lxterm /dev/ttyUSB1
|
||||
# lxterm /dev/ttyUSB1 --speed=2e6
|
||||
# lxterm /dev/ttyUSB1 --speed=1e6
|
||||
echo "Connect to FPGA thusly:" && \
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6" && \
|
||||
#lxterm /dev/ttyUSB1 --speed=1e6
|
||||
#lxterm /dev/ttyUSB2 --speed=1e6
|
||||
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,171 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Creates:
|
||||
# RISC-V 32-bit core running Linux with root filesystem for ECP5 FPGA.
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-vex-kernel-root-$FPGANOW) 2>>$FPGADIR/log/trellis-vex-kernel-root-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGASCRIPTS || exit
|
||||
|
||||
###############
|
||||
# Build LiteX #
|
||||
###############
|
||||
cd $FPGADIR/litex
|
||||
|
||||
# Update Buildroot
|
||||
echo "===================================== Update buildroot"
|
||||
cd buildroot && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
make clean && \
|
||||
# XXX Use custom linux.config
|
||||
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
|
||||
# XXX Set up rootfs overlay files defined here:
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
cp -a $FPGADIR/PATCH/rootfs_overlay \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
# XXX Use custom defconfig
|
||||
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
|
||||
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
|
||||
# 5m16s:
|
||||
make && \
|
||||
# XXX COPY OUTPUT
|
||||
# XXX *output/images/*
|
||||
# Since tftp server is remote, mount it locally for convenience:
|
||||
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
|
||||
cp -p output/images/Image /srv/tftp/Image && \
|
||||
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
|
||||
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
|
||||
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
|
||||
|
||||
cd ..
|
||||
|
||||
# Update litex
|
||||
echo "===================================== Update litex"
|
||||
# XXX BUILD
|
||||
cd litex && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
# BUILD VexRiscv.v HERE XXX
|
||||
cd litex/soc/cores/cpu/vexriscv/verilog && \
|
||||
# Remove older builds
|
||||
rm -f *.v && \
|
||||
# BUILD VEXRISCV
|
||||
# 1m8s:
|
||||
make && \
|
||||
cd ../../../../../.. && \
|
||||
# Build LiteX
|
||||
# 7 seconds:
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user && \
|
||||
cd .. && \
|
||||
#####################
|
||||
# Build RISC-V Core #
|
||||
#####################
|
||||
# XXX This build is done in above LiteX subdir
|
||||
# XXX So this is unused duplicate
|
||||
# XXX Should this really be built here earlier???
|
||||
# $FPGADIR/litex/litex/litex/soc/cores/cpu/vexriscv/verilog
|
||||
#
|
||||
# Update Vexrisc-verilog
|
||||
echo "===================================== Update vexrisc-verilog"
|
||||
# XXX BUILD
|
||||
cd Vexriscv-verilog && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
# XXX clean thusly?
|
||||
# 5 seconds:
|
||||
sbt clean reload && \
|
||||
# XXX Just checkout VexRiscv_LinuxNoDspFmax ?
|
||||
# sbt "runMain vexriscv.GenCoreDefault"
|
||||
# 10 seconds:
|
||||
sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux-minimal" && \
|
||||
# XXX OUTPUT FILES:
|
||||
# VexRiscv.v VexRiscv.yaml
|
||||
cd ..
|
||||
|
||||
########################
|
||||
# Build Linux on LiteX #
|
||||
########################
|
||||
|
||||
# Update Linux on LiteX Vexriscv
|
||||
echo "===================================== Update linux-on-litex-vexriscv"
|
||||
# XXX BUILD
|
||||
cd linux-on-litex-vexriscv && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
# Clean
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/__pycache__/ && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/build && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/rv32.dtb && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.d && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.o && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.bin && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.elf && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg && \
|
||||
# Custom config, set kernel boot line in this script
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
# TrellisBoard Patch to make.py
|
||||
patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff && \
|
||||
# TrellisBoard config
|
||||
cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg && \
|
||||
# motd :)
|
||||
cp -p $FPGADIR/PATCH/linux-on-litex-motd \
|
||||
buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd && \
|
||||
# motd date
|
||||
echo "motd date `date`" >> buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd
|
||||
# XXX BUILD
|
||||
# XXX Add output of Vexrisc.v and buildroot etc from above
|
||||
#
|
||||
#
|
||||
# 2m1s:
|
||||
./make.py --board=trellisboard --build
|
||||
|
||||
# XXX Copy to tftp server 1 file needed ?
|
||||
cp -p buildroot/rv32.dtb /srv/tftp/rv32.dtb && \
|
||||
# XXX copy to tftp server emulator.bin
|
||||
cp -p emulator/emulator.bin /srv/tftp/emulator.bin && \
|
||||
#
|
||||
#
|
||||
# Load image on FPGA
|
||||
# XXX busted:
|
||||
./make.py --board=trellisboard --load && \
|
||||
cd ..
|
||||
echo "Connect to FPGA thusly:" && \
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,19 @@
|
||||
#!/bin/bash
|
||||
|
||||
rm -rf /home/jebba/devel/FPGA/litex/linux-on-litex-vexriscv/build
|
||||
|
||||
cd /home/jebba/devel/FPGA/litex/linux-on-litex-vexriscv/
|
||||
./make.py --board=trellisboard --build
|
||||
./make.py --board=trellisboard --load
|
||||
|
||||
lxterm /dev/ttyUSB1 --speed=1e6
|
||||
|
||||
#openocd -f /home/jebba/devel/FPGA/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg -c "init; svf /home/jebba/devel/FPGA/litex/linux-on-litex-vexriscv/build/trellisboard/gateware/top.svf ; exit"
|
||||
|
||||
#echo "To boot Linux from SLOW serial run:"
|
||||
#echo "lxterm --images=/home/jebba/devel/FPGA/muh/jeboot.json /dev/ttyUSB1 --no-crc --speed=1e6"
|
||||
|
||||
#echo "To just connect run, then TFTP boot is fastest:"
|
||||
#echo "lxterm /dev/ttyUSB1 --speed=1e6"
|
||||
|
||||
|
||||
@ -0,0 +1,15 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/partner/targets/soc_basesoc_trellisboard
|
||||
|
||||
cd /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/partner/targets
|
||||
|
||||
./trellisboard.py --gateware-toolchain trellis
|
||||
|
||||
|
||||
openocd -f /home/jebba/devel/FPGA/muh/trellisboard.cfg -c "init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/partner/targets/soc_basesoc_trellisboard/gateware/top.svf ; exit"
|
||||
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
@ -0,0 +1,48 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
cd ~/devel/FPGA/litex/litex-boards/litex_boards/partner/targets
|
||||
|
||||
./trellisboard.py \
|
||||
--with-ethernet \
|
||||
--sys-clk-freq=75e6 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--cpu-variant=linux+no-dsp \
|
||||
--csr-csv=./csr_trellisboard.csv
|
||||
|
||||
exit 0
|
||||
openocd \
|
||||
-f ~/devel/FPGA/muh/trellisboard.cfg \
|
||||
-c "init; svf soc_ethernetsoc_trellisboard/gateware/top.svf ; exit"
|
||||
|
||||
#lxterm /dev/ttyUSB1 --speed=2e6
|
||||
#lxterm /dev/ttyUSB1 --speed=1e6
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
exit 0
|
||||
|
||||
TypeError: __init__() got multiple values for keyword argument 'integrated_rom_size'
|
||||
--integrated-rom-size=32768 \
|
||||
--integrated-rom-size=1 \
|
||||
--integrated-rom-size=0 \
|
||||
|
||||
ValueError: Memory region conflict between main_ram and main_ram
|
||||
--integrated-main-ram-size=131072 \
|
||||
--integrated-main-ram-size=32768 \
|
||||
--integrated-main-ram-size=536870912 \
|
||||
--integrated-main-ram-size=10 \
|
||||
--integrated-main-ram-size=9 \
|
||||
--integrated-main-ram-size=8 \
|
||||
|
||||
assert(min < max)
|
||||
--integrated-main-ram-size=1 \
|
||||
--integrated-main-ram-size=2 \
|
||||
--integrated-main-ram-size=3 \
|
||||
--integrated-main-ram-size=4 \
|
||||
--integrated-main-ram-size=7 \
|
||||
|
||||
BUILDS:
|
||||
--integrated-main-ram-size=0 \
|
||||
@ -0,0 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
# Set up tftp:
|
||||
cp -p /home/jebba/devel/FPGA/muh/BEST/tftp/* /srv/tftp/
|
||||
|
||||
# Set up SVF
|
||||
cp -p /home/jebba/devel/FPGA/muh/BEST/SVF/top.svf
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/BEST/openocd/trellisboard.cfg \
|
||||
-c "init; svf /home/jebba/devel/FPGA/muh/BEST/SVF/top.svf ; exit"
|
||||
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6"
|
||||
|
||||
lxterm /dev/ttyUSB2 --speed=1e6
|
||||
|
||||
@ -0,0 +1,18 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
# Set up tftp:
|
||||
cp -p /home/jebba/devel/FPGA/muh/TEST/tftp/* /srv/tftp/
|
||||
|
||||
# Set up SVF
|
||||
cp -p /home/jebba/devel/FPGA/muh/TEST/SVF/top.svf
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/TEST/openocd/trellisboard.cfg \
|
||||
-c "init; svf /home/jebba/devel/FPGA/muh/TEST/SVF/top.svf ; exit"
|
||||
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6"
|
||||
|
||||
lxterm /dev/ttyUSB2 --speed=1e6
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
#!/bin/bash
|
||||
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-rocket-$FPGANOW) 2>>$FPGADIR/log/trellis-rocket-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets
|
||||
|
||||
rm -rf soc_ethernetsoc_trellisboard
|
||||
|
||||
./trellisboard.py \
|
||||
--with-ethernet \
|
||||
--sys-clk-freq=60e6 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=rocket \
|
||||
--cpu-variant=linux \
|
||||
--csr-csv=./csr_trellisboard.csv
|
||||
|
||||
# --sys-clk-freq=75e6 \
|
||||
|
||||
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets/soc_ethernetsoc_trellisboard/gateware
|
||||
|
||||
openocd \
|
||||
-f $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg \
|
||||
-c "init; svf top.svf ; exit"
|
||||
|
||||
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6"
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
openocd -f /home/jebba/devel/FPGA/muh/trellisboard.cfg -c "init; svf /home/jebba/devel/forksand/fs-TrellisBoard/gateware/simple/demo.svf ; exit"
|
||||
|
||||
@ -0,0 +1,112 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Creates:
|
||||
# RISC-V 32-bit core running Linux with root filesystem for ECP5 FPGA.
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-kernel-root-$FPGANOW) 2>>$FPGADIR/log/trellis-kernel-root-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGASCRIPTS || exit
|
||||
|
||||
###############
|
||||
# Build LiteX #
|
||||
###############
|
||||
cd $FPGADIR/litex
|
||||
|
||||
# Update Buildroot
|
||||
echo "===================================== Update buildroot"
|
||||
cd buildroot && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
make clean && \
|
||||
# XXX Use custom linux.config
|
||||
cp -p $FPGADIR/PATCH/linux-fstrellis.config \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config
|
||||
# XXX Set up rootfs overlay files defined here:
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
cp -a $FPGADIR/PATCH/rootfs_overlay \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/rootfs_overlay
|
||||
# XXX Use custom defconfig
|
||||
cp -p $FPGADIR/PATCH/litex_vexriscv_fstrellis_defconfig \
|
||||
$FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig
|
||||
make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_fstrellis_defconfig \
|
||||
# 5m16s:
|
||||
make && \
|
||||
# XXX COPY OUTPUT
|
||||
# XXX *output/images/*
|
||||
# Since tftp server is remote, mount it locally for convenience:
|
||||
sshfs -o reconnect sparkle:/srv/tftp/ /srv/tftp/
|
||||
cp -p output/images/Image /srv/tftp/Image && \
|
||||
cp -p output/images/rootfs.cpio /srv/tftp/rootfs.cpio && \
|
||||
cp -p output/images/rootfs.tar /srv/tftp/rootfs.tar && \
|
||||
# Where dtb dts ? ./linux-on-litex-vexriscv/buildroot/rv32.dtb
|
||||
|
||||
cd ..
|
||||
|
||||
########################
|
||||
# Build Linux on LiteX #
|
||||
########################
|
||||
|
||||
# Update Linux on LiteX Vexriscv
|
||||
echo "===================================== Update linux-on-litex-vexriscv"
|
||||
# XXX BUILD
|
||||
cd linux-on-litex-vexriscv && \
|
||||
git branch -a && \
|
||||
git checkout master && \
|
||||
git reset --hard HEAD && \
|
||||
git status && \
|
||||
git log | head -1 | cut -f 2 -d " "
|
||||
#git pull && \
|
||||
#git submodule update && \
|
||||
# Clean
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/__pycache__/ && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/build && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/rv32.dtb && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/board/litex_vexriscv/linux-fstrellis.config && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/buildroot/configs/litex_vexriscv_fstrellis_defconfig && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.d && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/*.o && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.bin && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/emulator/emulator.elf && \
|
||||
rm -rf $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg && \
|
||||
# Custom config, set kernel boot line in this script
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
# TrellisBoard Patch to make.py
|
||||
patch -p0 < $FPGADIR/PATCH/0001-linuxonlitex-make.diff && \
|
||||
# TrellisBoard config
|
||||
cp -p $FPGADIR/PATCH/0000-trellisboard.cfg prog/trellisboard.cfg && \
|
||||
# motd :)
|
||||
cp -p $FPGADIR/PATCH/linux-on-litex-motd \
|
||||
buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd && \
|
||||
# motd date
|
||||
echo "motd date `date`" >> buildroot/board/litex_vexriscv/rootfs_overlay/etc/motd
|
||||
# 2m1s:
|
||||
./make.py --board=trellisboard --build
|
||||
|
||||
# XXX Copy to tftp server 1 file needed ?
|
||||
cp -p buildroot/rv32.dtb /srv/tftp/rv32.dtb && \
|
||||
# XXX copy to tftp server emulator.bin
|
||||
cp -p emulator/emulator.bin /srv/tftp/emulator.bin && \
|
||||
#
|
||||
# Load image on FPGA
|
||||
./make.py --board=trellisboard --load && \
|
||||
cd ..
|
||||
echo "Connect to FPGA thusly:" && \
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6" && \
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
#!/bin/bash
|
||||
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-vexriscv-$FPGANOW) 2>>$FPGADIR/log/trellis-vexriscv-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets
|
||||
|
||||
rm -rf soc_ethernetsoc_trellisboard
|
||||
|
||||
./trellisboard.py \
|
||||
--with-ethernet \
|
||||
--sys-clk-freq=75e6 \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--cpu-type=vexriscv \
|
||||
--cpu-variant=linux+no-dsp \
|
||||
--csr-csv=./csr_trellisboard.csv
|
||||
|
||||
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets/soc_ethernetsoc_trellisboard/gateware
|
||||
|
||||
openocd \
|
||||
-f $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg \
|
||||
-c "init; svf top.svf ; exit"
|
||||
|
||||
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6"
|
||||
echo "lxterm /dev/ttyUSB2 --speed=2e6"
|
||||
echo "lxterm /dev/ttyUSB2 --speed=115200"
|
||||
echo "lxterm /dev/ttyUSB2"
|
||||
|
||||
exit 0
|
||||
|
||||
|
||||
@ -0,0 +1,29 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-vexriscv-load-$FPGANOW) 2>>$FPGADIR/log/trellis-vexriscv-load-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
#######################
|
||||
# Load Linux on LiteX #
|
||||
#######################
|
||||
cd $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
echo "===================================== Update linux-on-litex-vexriscv"
|
||||
# Load image on FPGA
|
||||
./make.py --board=trellisboard --load
|
||||
|
||||
echo "Connect to FPGA thusly:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=1e6"
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6"
|
||||
lxterm /dev/ttyUSB1 --speed=1e6
|
||||
#lxterm /dev/ttyUSB2 --speed=1e6
|
||||
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,27 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/trellis-vexriscv-load-$FPGANOW) 2>>$FPGADIR/log/trellis-vexriscv-load-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
#######################
|
||||
# Load Linux on LiteX #
|
||||
#######################
|
||||
cd $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
echo "===================================== Update linux-on-litex-vexriscv"
|
||||
|
||||
# use custom json2dts.py that sets kernel boot line
|
||||
cp -p $FPGADIR/PATCH/json2dts.py $FPGADIR/litex/linux-on-litex-vexriscv
|
||||
|
||||
# make image on FPGA
|
||||
./make.py --board=trellisboard --build
|
||||
|
||||
exit 0
|
||||
|
||||
@ -0,0 +1,22 @@
|
||||
#!/bin/bash
|
||||
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
#exec > >(tee $FPGADIR/log/trellis-vexriscv-$FPGANOW) 2>>$FPGADIR/log/trellis-vexriscv-$FPGANOW
|
||||
|
||||
set -x
|
||||
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets/soc_ethernetsoc_trellisboard/gateware
|
||||
|
||||
openocd \
|
||||
-f $FPGADIR/litex/linux-on-litex-vexriscv/prog/trellisboard.cfg \
|
||||
-c "init; svf top.svf ; exit"
|
||||
|
||||
|
||||
echo "lxterm /dev/ttyUSB2 --speed=1e6"
|
||||
|
||||
@ -0,0 +1,48 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Directory where everything is stored
|
||||
FPGADIR=/home/jebba/devel/FPGA
|
||||
# Directory of scripts
|
||||
FPGASCRIPTS=$FPGADIR/muh
|
||||
# Timestamp
|
||||
FPGANOW=`date +%Y%m%d-%H%M%S`
|
||||
|
||||
# Log script
|
||||
exec > >(tee $FPGADIR/log/ulx3s-$FPGANOW) 2>>$FPGADIR/log/ulx3s-$FPGANOW
|
||||
|
||||
set -x
|
||||
cd $FPGADIR/litex/litex-boards/litex_boards/partner/targets
|
||||
|
||||
./ulx3s.py \
|
||||
--gateware-toolchain=trellis \
|
||||
--gateware-toolchain-path=/usr/local \
|
||||
--device=LFE5UM-85F \
|
||||
--sys-clk-freq=50e6 \
|
||||
--cpu-type=vexriscv \
|
||||
--cpu-variant=linux+no-dsp \
|
||||
--csr-csv=./csr_ulx3s.csv
|
||||
|
||||
|
||||
# ujprog $FPGADIR/litex/litex-boards/litex_boards/partner/targets/soc_basesoc_ulx3s/gateware/top.svf
|
||||
|
||||
exit 0
|
||||
|
||||
# Flash mofo:
|
||||
openocd \
|
||||
-f $FPGADIR/PATCH/ulx3s.cfg \
|
||||
-c "init; svf soc_basesoc_ulx3s/gateware/top.svf ; exit"
|
||||
|
||||
|
||||
|
||||
exit 0
|
||||
|
||||
--device=LFE5U-85F \
|
||||
-f $FPGADIR/litex/linux-on-litex-vexriscv/prog/ulx3s.cfg \
|
||||
|
||||
#
|
||||
--sdram-module SDRAM_MODULE
|
||||
SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16
|
||||
(default=MT48LC16M16)
|
||||
|
||||
#
|
||||
lxterm /dev/ttyUSB0 --speed=1e6
|
||||
@ -0,0 +1,61 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
# Wt
|
||||
cd /home/jebba/devel/FPGA/litex/litex/litex/boards/targets
|
||||
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5
|
||||
rm -rf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_ethernetsoc_versa_ecp5
|
||||
|
||||
echo
|
||||
echo "NOW BUILDING"
|
||||
echo
|
||||
|
||||
# Build .svf
|
||||
./versa_ecp5.py \
|
||||
--with-ethernet \
|
||||
--sys-clk-freq 66e6 \
|
||||
--gateware-toolchain trellis \
|
||||
--gateware-toolchain-path /usr/local \
|
||||
--cpu-type rocket \
|
||||
--cpu-variant linux \
|
||||
--csr-csv ./csr_ecp5versa.csv \
|
||||
|| exit
|
||||
|
||||
# If you add/remove ethernet, also need to change .svf below
|
||||
# --with-ethernet \
|
||||
# --cpu-type=rocket
|
||||
# --sys-clk-freq=60e6 \
|
||||
# --cpu-variant=linux \
|
||||
|
||||
|
||||
exit 0
|
||||
|
||||
echo
|
||||
echo "NOW FLASHING"
|
||||
echo
|
||||
|
||||
openocd \
|
||||
-f /home/jebba/devel/FPGA/muh/ecp5-versa5g.cfg \
|
||||
-c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|| exit
|
||||
# No ethernet
|
||||
# XXX UPDATE
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex/litex/boards/targets/soc_basesoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
# With ethernet
|
||||
# -c "transport select jtag; init; svf /home/jebba/devel/FPGA/litex/litex-boards/litex_boards/official/targets/soc_ethernetsoc_versa_ecp5/gateware/top.svf; exit" \
|
||||
|
||||
|
||||
echo "Running:"
|
||||
echo "lxterm /dev/ttyUSB1"
|
||||
echo "Hit ctrl-c twice to bail"
|
||||
echo
|
||||
echo "If that lxterm doesn't connect try like this:"
|
||||
echo "lxterm /dev/ttyUSB1 --speed=2e6"
|
||||
|
||||
echo
|
||||
echo "NOW CONNECTING"
|
||||
echo
|
||||
|
||||
lxterm /dev/ttyUSB1
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
PATH=$PATH:/home/jebba/devel/litex/toolchain/bin
|
||||
|
||||
cd litedram
|
||||
./setup.py build
|
||||
./setup.py install --user
|
||||
etc....
|
||||
@ -0,0 +1,32 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
cd icestorm
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
cd ..
|
||||
|
||||
cd arachne-pnr
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
cd ..
|
||||
|
||||
cd prjtrellis
|
||||
cd libtrellis
|
||||
cmake -DCMAKE_INSTALL_PREFIX=/usr/local .
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
cd ../..
|
||||
|
||||
cd nextpnr
|
||||
#cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local .
|
||||
cmake -DARCH=ecp5 -DCMAKE_INSTALL_PREFIX=/usr/local .
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
cd ..
|
||||
|
||||
cd yosys
|
||||
make -j$(nproc)
|
||||
sudo make install
|
||||
cd ..
|
||||
@ -0,0 +1,66 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import os
|
||||
import sys
|
||||
from collections import OrderedDict
|
||||
|
||||
|
||||
current_path = os.path.dirname(os.path.realpath(__file__))
|
||||
|
||||
# name, (url, recursive clone, develop)
|
||||
repos = [
|
||||
# HDL
|
||||
("migen", ("https://github.com/m-labs/", True, True)),
|
||||
|
||||
# LiteX SoC builder
|
||||
("litex", ("https://github.com/enjoy-digital/", True, True)),
|
||||
|
||||
# LiteX cores ecosystem
|
||||
("liteeth", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litedram", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litepcie", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litesata", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litesdcard", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("liteiclink", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litevideo", ("https://github.com/enjoy-digital/", False, True)),
|
||||
("litescope", ("https://github.com/enjoy-digital/", False, True)),
|
||||
|
||||
# LiteX boards support
|
||||
("litex-boards", ("https://github.com/litex-hub/", False, True)),
|
||||
]
|
||||
repos = OrderedDict(repos)
|
||||
|
||||
if len(sys.argv) < 2:
|
||||
print("Available commands:")
|
||||
print("- init")
|
||||
print("- install (add --user to install to user directory)")
|
||||
print("- update")
|
||||
exit()
|
||||
|
||||
if "init" in sys.argv[1:]:
|
||||
for name in repos.keys():
|
||||
url, need_recursive, need_develop = repos[name]
|
||||
# clone repo (recursive if needed)
|
||||
print("[cloning " + name + "]...")
|
||||
full_url = url + name
|
||||
opts = "--recursive" if need_recursive else ""
|
||||
os.system("git clone " + full_url + " " + opts)
|
||||
|
||||
if "install" in sys.argv[1:]:
|
||||
for name in repos.keys():
|
||||
url, need_recursive, need_develop = repos[name]
|
||||
# develop if needed
|
||||
print("[installing " + name + "]...")
|
||||
if need_develop:
|
||||
os.chdir(os.path.join(current_path, name))
|
||||
if "--user" in sys.argv[1:]:
|
||||
os.system("python3 setup.py develop --user")
|
||||
else:
|
||||
os.system("python3 setup.py develop")
|
||||
|
||||
if "update" in sys.argv[1:]:
|
||||
for name in repos.keys():
|
||||
# update
|
||||
print("[updating " + name + "]...")
|
||||
os.chdir(os.path.join(current_path, name))
|
||||
os.system("git pull")
|
||||
@ -0,0 +1,29 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Manual updates:
|
||||
# toolchain
|
||||
|
||||
set -x
|
||||
|
||||
# Just pull, don't build
|
||||
# Git pull
|
||||
for i in buildroot pcie_screamer Vexriscv-verilog versa_ecp5 litex-buildenv litex-buildenv-udev linux-on-litex-vexriscv-prebuilt linux-on-litex-vexriscv
|
||||
do echo "Updating $i"
|
||||
cd $i
|
||||
#git checkout master
|
||||
git pull
|
||||
cd ..
|
||||
done
|
||||
|
||||
cd linux-on-litex-vexriscv ; git checkout fs-trellis
|
||||
|
||||
# Python, git pull, build, install locally
|
||||
for i in migen litedram liteeth liteiclink litejesd204b litepcie litesata litescope litesdcard litevideo litex-boards litex
|
||||
do echo "Updating $i"
|
||||
cd $i
|
||||
git pull
|
||||
./setup.py clean && ./setup.py build && ./setup.py install --user || exit
|
||||
cd ..
|
||||
done
|
||||
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
#!/bin/bash
|
||||
|
||||
set -x
|
||||
|
||||
cd icestorm && \
|
||||
git pull && \
|
||||
make clean && \
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
cd arachne-pnr && \
|
||||
git pull && \
|
||||
make clean && \
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
cd prjtrellis && \
|
||||
git pull && \
|
||||
cd libtrellis && \
|
||||
make clean && \
|
||||
cmake -DCMAKE_INSTALL_PREFIX=/usr/local . && \
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ../..
|
||||
|
||||
cd nextpnr && \
|
||||
git pull && \
|
||||
make clean && \
|
||||
#cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . && \
|
||||
cmake -DARCH=ecp5 -DCMAKE_INSTALL_PREFIX=/usr/local . && \
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
cd yosys && \
|
||||
git pull && \
|
||||
make clean && \
|
||||
make -j$(nproc) && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
cd openocd && \
|
||||
git pull && \
|
||||
make clean && \
|
||||
make && \
|
||||
sudo make install || exit
|
||||
cd ..
|
||||
|
||||
Loading…
Reference in new issue