--load works

scripts/forksand-trellis-all

@@ -510,17 +510,16 @@ cp -p ../pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/ext/Vex
 #
 #
 # Load image on FPGA
-# XXX busted:
 ./make.py --board=trellisboard --load &&				\
 ######################
 # Load image on FPGA #
 ######################
 # Use this to flash since make.py broken:
-cd $FPGADIR
-openocd									\
-	-f ./prjtrellis/misc/openocd/trellisboard.cfg			\
-	-c  "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/trellisboard.svf ; exit"
-cd ..
+#cd $FPGADIR
+#openocd									\
+#	-f ./prjtrellis/misc/openocd/trellisboard.cfg			\
+#	-c  "init; svf litex/linux-on-litex-vexriscv/build/trellisboard/gateware/trellisboard.svf ; exit"
+#cd ..
 ###################
 # Connect to FPGA #
 ###################