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hardware/mainboard: Working on 3D

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Signed-off-by: David Shah <dave@ds0.me>
master
David Shah 6 years ago
parent 4c7e228c77
commit 61cf6c41d1
2 changed files with 886 additions and 816 deletions
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1591
hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb
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@ -1537,6 +1537,454 @@
(add_net ~PERST)
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF66AD3)
(at 135 30 180)
(path /61FAF948/64AB9BC6)
(fp_text reference J7 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT2 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 545 "Net-(J7-Pad38)"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 544 "/FPGA IO/EXT2_11-"))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 543 "/FPGA IO/EXT2_11+"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 542 "/FPGA IO/EXT2_10-"))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 541 "/FPGA IO/EXT2_10+"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 540 "/FPGA IO/EXT2_9-"))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 539 "/FPGA IO/EXT2_9+"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 538 "/FPGA IO/EXT2_8-"))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 537 "/FPGA IO/EXT2_8+"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 536 "/FPGA IO/EXT2_7-"))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 535 "/FPGA IO/EXT2_7+"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 534 "/FPGA IO/EXT2_6-"))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 533 "/FPGA IO/EXT2_6+"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 532 "/FPGA IO/EXT2_5-"))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 531 "/FPGA IO/EXT2_5+"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 530 "/FPGA IO/EXT2_4-"))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 529 "/FPGA IO/EXT2_4+"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 528 "/FPGA IO/EXT2_3-"))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 527 "/FPGA IO/EXT2_3+"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 526 "/FPGA IO/EXT2_2-"))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 525 "/FPGA IO/EXT2_2+"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 524 "/FPGA IO/EXT2_1-"))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 523 "/FPGA IO/EXT2_1+"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 522 "/FPGA IO/EXT2_0-"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 521 "/FPGA IO/EXT2_0+"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(model /home/david/3d/c-4-1734839-0-c-3d.stp
(offset (xyz 0 -5 1))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF66BA8)
(at 106 30 180)
(path /61FAF948/635A137F)
(fp_text reference J6 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT1 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 496 "Net-(J6-Pad38)"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 497 "/FPGA IO/EXT1_11-"))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 498 "/FPGA IO/EXT1_11+"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 499 "/FPGA IO/EXT1_10-"))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 500 "/FPGA IO/EXT1_10+"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 501 "/FPGA IO/EXT1_9-"))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 502 "/FPGA IO/EXT1_9+"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 503 "/FPGA IO/EXT1_8-"))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 504 "/FPGA IO/EXT1_8+"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 505 "/FPGA IO/EXT1_7-"))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 506 "/FPGA IO/EXT1_7+"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 507 "/FPGA IO/EXT1_6-"))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 508 "/FPGA IO/EXT1_6+"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 509 "/FPGA IO/EXT1_5-"))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 510 "/FPGA IO/EXT1_5+"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 511 "/FPGA IO/EXT1_4-"))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 512 "/FPGA IO/EXT1_4+"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 513 "/FPGA IO/EXT1_3-"))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 514 "/FPGA IO/EXT1_3+"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 515 "/FPGA IO/EXT1_2-"))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 516 "/FPGA IO/EXT1_2+"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 517 "/FPGA IO/EXT1_1-"))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 518 "/FPGA IO/EXT1_1+"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 519 "/FPGA IO/EXT1_0-"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 520 "/FPGA IO/EXT1_0+"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(model /home/david/3d/c-4-1734839-0-c-3d.stp
(offset (xyz 0 -5 1))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF675A7)
(at 164 30 180)
(path /61FAF948/65FA91E0)
(fp_text reference J8 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT3 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 495 "Net-(J8-Pad38)"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 494 "/FPGA IO/EXT3_11-"))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 493 "/FPGA IO/EXT3_11+"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 492 "/FPGA IO/EXT3_10-"))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 491 "/FPGA IO/EXT3_10+"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 490 "/FPGA IO/EXT3_9-"))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 489 "/FPGA IO/EXT3_9+"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 488 "/FPGA IO/EXT3_8-"))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 487 "/FPGA IO/EXT3_8+"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 486 "/FPGA IO/EXT3_7-"))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 485 "/FPGA IO/EXT3_7+"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 484 "/FPGA IO/EXT3_6-"))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 483 "/FPGA IO/EXT3_6+"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 482 "/FPGA IO/EXT3_5-"))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 481 "/FPGA IO/EXT3_5+"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 480 "/FPGA IO/EXT3_4-"))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 479 "/FPGA IO/EXT3_4+"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 478 "/FPGA IO/EXT3_3-"))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 477 "/FPGA IO/EXT3_3+"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 476 "/FPGA IO/EXT3_2-"))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 475 "/FPGA IO/EXT3_2+"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 474 "/FPGA IO/EXT3_1-"))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 473 "/FPGA IO/EXT3_1+"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 472 "/FPGA IO/EXT3_0-"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 471 "/FPGA IO/EXT3_0+"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(model /home/david/3d/c-4-1734839-0-c-3d.stp
(offset (xyz 0 -5 1))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF676D0)
(at 77 30 180)
(path /61FAF948/62664D22)
(fp_text reference J5 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT0 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 446 "Net-(J5-Pad38)"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 447 "/FPGA IO/EXT0_11-"))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 448 "/FPGA IO/EXT0_11+"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 449 "/FPGA IO/EXT0_10-"))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 450 "/FPGA IO/EXT0_10+"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 451 "/FPGA IO/EXT0_9-"))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 452 "/FPGA IO/EXT0_9+"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 453 "/FPGA IO/EXT0_8-"))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 454 "/FPGA IO/EXT0_8+"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 455 "/FPGA IO/EXT0_7-"))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 456 "/FPGA IO/EXT0_7+"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 457 "/FPGA IO/EXT0_6-"))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 458 "/FPGA IO/EXT0_6+"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 459 "/FPGA IO/EXT0_5-"))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 460 "/FPGA IO/EXT0_5+"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 461 "/FPGA IO/EXT0_4-"))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 462 "/FPGA IO/EXT0_4+"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 463 "/FPGA IO/EXT0_3-"))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 464 "/FPGA IO/EXT0_3+"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 465 "/FPGA IO/EXT0_2-"))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 466 "/FPGA IO/EXT0_2+"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 467 "/FPGA IO/EXT0_1-"))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 468 "/FPGA IO/EXT0_1+"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 469 "/FPGA IO/EXT0_0-"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 470 "/FPGA IO/EXT0_0+"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(model /home/david/3d/c-4-1734839-0-c-3d.stp
(offset (xyz 0 -5 1))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module Capacitor_SMD:C_0402_1005Metric (layer B.Cu) (tedit 5B301BBE) (tstamp 5BFDC1B2)
(at 164.7 94.9)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
@ -2481,10 +2929,10 @@
(net 24 GND))
(pad 1 smd rect (at -3.975 -2.25 180) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_B3S-1000.wrl
(model /home/david/3d/b3s-1000.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz -90 0 90))
)
)
@ -2528,10 +2976,10 @@
(net 100 BTN3))
(pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask)
(net 100 BTN3))
(model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_B3S-1000.wrl
(model /home/david/3d/b3s-1000.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz -90 0 90))
)
)
@ -2575,10 +3023,10 @@
(net 99 BTN2))
(pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask)
(net 99 BTN2))
(model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_B3S-1000.wrl
(model /home/david/3d/b3s-1000.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz -90 0 90))
)
)
@ -2627,6 +3075,11 @@
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model /home/david/3d/b3s-1000.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 90))
)
)
(module Button_Switch_SMD:SW_SPST_B3S-1000 (layer F.Cu) (tedit 5A02FC95) (tstamp 5BF63845)
@ -2669,10 +3122,10 @@
(net 98 BTN0))
(pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask)
(net 98 BTN0))
(model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_B3S-1000.wrl
(model /home/david/3d/b3s-1000.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz -90 0 90))
)
)
@ -11309,8 +11762,8 @@
(net 161 USD_D1))
(pad 9 smd rect (at -5.875 -7.725 90) (size 0.7 1.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(model ${KISYS3DMOD}/Connector_Card.3dshapes/microSD_HC_Hirose_DM3AT-SF-PEJM5.wrl
(offset (xyz 2.774999958223682 7.124999892393237 0))
(model /home/david/3d/DM3AT-SF-PEJM5.stp
(offset (xyz -165.25 -154 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
@ -13454,6 +13907,11 @@
(net 485 "/FPGA IO/EXT3_7+"))
(pad B1 smd circle (at -12.4 -11.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 479 "/FPGA IO/EXT3_4+"))
(model /home/david/3d/cabga756.stp
(offset (xyz -13.5 -13.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module "Custom Parts:Crystal_Epsom_TSX-3225" (layer B.Cu) (tedit 5BF5790A) (tstamp 5BF67623)
@ -13613,6 +14071,11 @@
(net 81 DIP_SW1))
(pad 1 smd rect (at -4.445 2.54 180) (size 0.76 1.6) (layers F.Cu F.Paste F.Mask)
(net 82 DIP_SW0))
(model /home/david/3d/CHP-081TA.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:FuseHolder_SMD_Shurter_0031.7701.11" (layer F.Cu) (tedit 5BF57487) (tstamp 5BF67D30)
@ -13630,6 +14093,11 @@
(net 597 "Net-(F2-Pad2)"))
(pad 1 smd rect (at -4 0) (size 5 6) (layers F.Cu F.Paste F.Mask)
(net 170 +12V))
(model /home/david/3d/0031-7701-11.STEP
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 90))
)
)
(module "Custom Parts:FuseHolder_SMD_Shurter_0031.7701.11" (layer F.Cu) (tedit 5BF57487) (tstamp 5BF67FA6)
@ -13647,6 +14115,11 @@
(net 126 PCIe_12V))
(pad 1 smd rect (at -4 0 180) (size 5 6) (layers F.Cu F.Paste F.Mask)
(net 170 +12V))
(model /home/david/3d/0031-7701-11.STEP
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 90))
)
)
(module "Custom Parts:L_CoilCraft_XAL60xx" (layer F.Cu) (tedit 5BF5A7C9) (tstamp 5BF677A7)
@ -13666,6 +14139,11 @@
(net 216 "Net-(C8-Pad1)"))
(pad 2 smd rect (at 2.02 0 90) (size 1.43 5.5) (layers F.Cu F.Paste F.Mask)
(net 17 +5V))
(model /home/david/3d/Coilcraft-XAL6030.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:Molex_HDMI_A_47151-0001" (layer F.Cu) (tedit 5BF56BA5) (tstamp 5BF66772)
@ -13731,60 +14209,19 @@
(net 24 GND))
(pad SH thru_hole oval (at 7.25 8.02 270) (size 1.5 2.3) (drill oval 0.9 1.7) (layers *.Cu *.Mask)
(net 24 GND))
(pad SH thru_hole oval (at -7.25 8.02 270) (size 1.5 2.3) (drill oval 0.9 1.7) (layers *.Cu *.Mask)
(net 24 GND))
(model /home/david/3d/471510001.stp
(offset (xyz 0 -12.5 3))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:Molex_SATA_047080-4001" (layer F.Cu) (tedit 5BF5688A) (tstamp 5BF667D2)
(at 229.5 80.5 90)
(path /5C060E84/5C4A25FF)
(fp_text reference P1 (at 6.7 -1.6 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SATA (at 0 5.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -9.3 9.2) (end -9.3 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -9.3 -0.8) (end -4.5 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 10) (end 8.3 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 -0.8) (end 4.4 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 6.6 10.8) (end 8.3 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 10.8) (end 8.3 10) (layer F.SilkS) (width 0.15))
(fp_line (start 0.2 10.8) (end 5.6 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start 5.6 10.8) (end 6.6 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 10.8) (end -6.1 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 10.8) (end -9.3 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -9.3 10.8) (end -9.3 9.2) (layer F.SilkS) (width 0.15))
(fp_line (start -6.1 10.8) (end 0.3 10.8) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at 3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 2 smd rect (at 2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 426 "/PCIe + SATA/SATA0_A+"))
(pad 3 smd rect (at 1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 427 "/PCIe + SATA/SATA0_A-"))
(pad 4 smd rect (at 0 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 5 smd rect (at -1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 428 "/PCIe + SATA/DCU1_RX0-"))
(pad 6 smd rect (at -2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 429 "/PCIe + SATA/DCU1_RX0+"))
(pad 7 smd rect (at -3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad S thru_hole rect (at 6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(pad S thru_hole rect (at -6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(pad SH thru_hole oval (at -7.25 8.02 270) (size 1.5 2.3) (drill oval 0.9 1.7) (layers *.Cu *.Mask)
(net 24 GND))
(model /home/david/3d/471510001.stp
(offset (xyz 0 -12.5 3))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:Molex_SATA_047080-4001" (layer F.Cu) (tedit 5BF5688A) (tstamp 5BF6681A)
(at 229.5 61.5 90)
(path /5C060E84/5C4A273B)
(fp_text reference P2 (at 6.7 -1.6 90) (layer F.SilkS)
(module "Custom Parts:Molex_SATA_047080-4001" (layer F.Cu) (tedit 5BF5688A) (tstamp 5BF667D2)
(at 229.5 80.5 90)
(path /5C060E84/5C4A25FF)
(fp_text reference P1 (at 6.7 -1.6 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SATA (at 0 5.9 90) (layer F.Fab)
@ -13805,762 +14242,385 @@
(pad 1 smd rect (at 3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 2 smd rect (at 2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 422 "/PCIe + SATA/SATA1_A+"))
(net 426 "/PCIe + SATA/SATA0_A+"))
(pad 3 smd rect (at 1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 423 "/PCIe + SATA/SATA1_A-"))
(net 427 "/PCIe + SATA/SATA0_A-"))
(pad 4 smd rect (at 0 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 5 smd rect (at -1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 424 "/PCIe + SATA/DCU1_RX1-"))
(net 428 "/PCIe + SATA/DCU1_RX0-"))
(pad 6 smd rect (at -2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 425 "/PCIe + SATA/DCU1_RX1+"))
(pad 7 smd rect (at -3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad S thru_hole rect (at 6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(pad S thru_hole rect (at -6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
)
(module "Custom Parts:OSC_IDT_XU_5x3.2mm" (layer F.Cu) (tedit 5BF572F5) (tstamp 5BF66861)
(at 145.4 45.5 90)
(path /61FAF948/6249D25D)
(fp_text reference U26 (at 0.3 3.3 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value XL_XO_LVDS (at 0 -2.7 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.3 1.9) (end -1.6 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 2.2) (end -1 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1 2.2) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8 1.6) (end -2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 1.6) (end -2.5 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 -1.6) (end -1.8 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.6 -1.6) (end 0.7 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -1.6) (end -0.6 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.6 1.6) (end -0.7 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.7 1.6) (end 0.6 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 1.6) (end 1.9 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 1.6) (end 1.8 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 1.8 -1.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 579 "Net-(U26-Pad1)"))
(pad 2 smd rect (at 0 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 580 "Net-(U26-Pad2)"))
(pad 3 smd rect (at 1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at 1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 581 "/FPGA IO/CLK100+"))
(pad 5 smd rect (at 0 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 582 "/FPGA IO/CLK100-"))
(pad 6 smd rect (at -1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 12 +3V3))
)
(module "Custom Parts:OSC_IDT_XU_5x3.2mm" (layer F.Cu) (tedit 5BF572F5) (tstamp 5BF668A6)
(at 124.3 101.9 90)
(path /5C060E84/5C744CC2)
(fp_text reference U14 (at 0.3 3.3 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value " XUL535150.000JS6I8" (at 0 -2.7 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.3 1.9) (end -1.6 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 2.2) (end -1 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1 2.2) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8 1.6) (end -2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 1.6) (end -2.5 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 -1.6) (end -1.8 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.6 -1.6) (end 0.7 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -1.6) (end -0.6 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.6 1.6) (end -0.7 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.7 1.6) (end 0.6 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 1.6) (end 1.9 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 1.6) (end 1.8 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 1.8 -1.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 578 "Net-(U14-Pad1)"))
(pad 2 smd rect (at 0 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 577 "Net-(U14-Pad2)"))
(pad 3 smd rect (at 1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at 1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 120 "/PCIe + SATA/CLK150M+"))
(pad 5 smd rect (at 0 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 115 "/PCIe + SATA/CLK150M-"))
(pad 6 smd rect (at -1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 416 "Net-(C111-Pad1)"))
)
(module "Custom Parts:PCIe_EDGE_x4" locked (layer F.Cu) (tedit 5BF55C2C) (tstamp 5BF6693F)
(at 92.9 131.4)
(path /5C060E84/5C060EE2)
(fp_text reference P3 (at 0 -7.35) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PCIe_x4_EDGE (at 0 -5.08) (layer Edge.Cuts)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 4.5 -3.95) (end 3.55 -3.95) (angle 180) (layer Edge.Cuts) (width 0.15))
(fp_line (start 5.45 -3.95) (end 5.45 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.55 3.5) (end -6.9 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.55 -3.95) (end 3.55 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 5.45 3.5) (end 26.65 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 3.5) (end 26.65 -3.2) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 3.5) (end -7.65 -2.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 3.5) (end -6.9 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.7 -107.65) (end 105.4 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_arc (start -9.475 -7.425) (end -11.3 -7.425) (angle 180) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 -7.425) (end -7.65 -2.47) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -1) (end -11.9 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -2.8) (end -11.3 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -7.2) (end -11.3 -2.8) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -7.45) (end -11.3 -7.2) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.9 -1) (end -19.3 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -107.65) (end 3.7 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -1) (end -52.65 -106.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -37.65 -1) (end -52.65 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -37.65 -9.25) (end -37.65 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -9.25) (end -37.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -1) (end -19.3 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -107.65) (end -19.3 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -106.65) (end -52.65 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 -9.25) (end 76.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 -3.2) (end 26.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 76.6 -9.25) (end 79.4 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.4 -9.25) (end 79.4 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 92.1 -1.88) (end 92.1 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.9 0.55) (end 90.71 0.55) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.4 -4.45) (end 79.4 0.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start 88.15 -9.25) (end 105.4 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 86.4 -6.2) (end 86.4 -7.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 92.1 -4.45) (end 88.15 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.9 0.55) (end 79.4 0.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start 90.7 0.55) (end 92.1 -1.88) (layer Edge.Cuts) (width 0.15))
(fp_arc (start 88.15 -7.5) (end 88.15 -9.25) (angle -90) (layer Edge.Cuts) (width 0.15))
(fp_arc (start 88.15 -6.2) (end 86.4 -6.2) (angle -90) (layer Edge.Cuts) (width 0.15))
(pad M thru_hole circle (at -45.1 -91.2) (size 5 5) (drill 3.18) (layers *.Cu *.Mask))
(pad M thru_hole circle (at -45.15 -5.85) (size 5 5) (drill 3.18) (layers *.Cu *.Mask))
(pad A32 smd rect (at 26 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 576 "Net-(P3-PadA32)"))
(pad A31 smd rect (at 25 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A30 smd rect (at 24 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 575 "Net-(P3-PadA30)"))
(pad A29 smd rect (at 23 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 574 "Net-(P3-PadA29)"))
(pad A28 smd rect (at 22 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A27 smd rect (at 21 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A26 smd rect (at 20 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 573 "Net-(P3-PadA26)"))
(pad A25 smd rect (at 19 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 572 "Net-(P3-PadA25)"))
(pad A24 smd rect (at 18 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A23 smd rect (at 17 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A22 smd rect (at 16 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 433 "/PCIe + SATA/PCIe_HSI1-"))
(pad A21 smd rect (at 15 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 432 "/PCIe + SATA/PCIe_HSI1+"))
(pad A20 smd rect (at 14 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A19 smd rect (at 13 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 571 "Net-(P3-PadA19)"))
(pad A18 smd rect (at 12 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A17 smd rect (at 11 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 431 "/PCIe + SATA/PCIe_HSI0-"))
(pad A16 smd rect (at 10 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 430 "/PCIe + SATA/PCIe_HSI0+"))
(pad A15 smd rect (at 9 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A14 smd rect (at 8 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 125 "/PCIe + SATA/PCIe_REFCLK-"))
(pad A13 smd rect (at 7 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 124 "/PCIe + SATA/PCIe_REFCLK+"))
(pad A12 smd rect (at 6 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A11 smd rect (at 3 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 129 "Net-(P3-PadA11)"))
(pad A10 smd rect (at 2 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 570 "Net-(P3-PadA10)"))
(pad A9 smd rect (at 1 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 569 "Net-(P3-PadA9)"))
(pad A8 smd rect (at 0 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 568 "Net-(P3-PadA8)"))
(pad A7 smd rect (at -1 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 567 "Net-(P3-PadA7)"))
(pad A6 smd rect (at -2 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 566 "Net-(P3-PadA6)"))
(pad A5 smd rect (at -3 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 565 "Net-(P3-PadA5)"))
(pad A4 smd rect (at -4 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad A3 smd rect (at -5 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 126 PCIe_12V))
(pad A2 smd rect (at -6 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 126 PCIe_12V))
(pad A1 smd rect (at -7 -0.5) (size 0.75 3.2) (layers B.Cu B.Paste B.Mask)
(net 564 "/PCIe + SATA/~PRSNT1"))
(pad B32 smd rect (at 26 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B31 smd rect (at 25 -0.5) (size 0.75 3.2) (layers F.Cu F.Paste F.Mask)
(net 563 "/PCIe + SATA/~PRSNT2~_X4"))
(pad B30 smd rect (at 24 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 562 "Net-(P3-PadB30)"))
(pad B29 smd rect (at 23 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B28 smd rect (at 22 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 561 "Net-(P3-PadB28)"))
(pad B27 smd rect (at 21 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 560 "Net-(P3-PadB27)"))
(pad B26 smd rect (at 20 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B25 smd rect (at 19 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B24 smd rect (at 18 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 559 "Net-(P3-PadB24)"))
(pad B23 smd rect (at 17 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 558 "Net-(P3-PadB23)"))
(pad B22 smd rect (at 16 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B21 smd rect (at 15 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B20 smd rect (at 14 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 437 "/PCIe + SATA/DCU0_RX1-"))
(pad B19 smd rect (at 13 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 436 "/PCIe + SATA/DCU0_RX1+"))
(pad B18 smd rect (at 12 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B17 smd rect (at 11 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 557 "/PCIe + SATA/~PRSNT2~_X1"))
(pad B16 smd rect (at 10 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B15 smd rect (at 9 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 435 "/PCIe + SATA/DCU0_RX0-"))
(pad B14 smd rect (at 8 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 434 "/PCIe + SATA/DCU0_RX0+"))
(pad B13 smd rect (at 7 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 429 "/PCIe + SATA/DCU1_RX0+"))
(pad 7 smd rect (at -3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad B12 smd rect (at 6 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 556 "Net-(P3-PadB12)"))
(pad B11 smd rect (at 3 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 555 PCIe_~WAKE))
(pad B10 smd rect (at 2 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 554 "Net-(P3-PadB10)"))
(pad B9 smd rect (at 1 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 553 "Net-(P3-PadB9)"))
(pad B8 smd rect (at 0 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 552 "Net-(P3-PadB8)"))
(pad B7 smd rect (at -1 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(pad S thru_hole rect (at 6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(pad B6 smd rect (at -2 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 551 "Net-(P3-PadB6)"))
(pad B5 smd rect (at -3 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 550 "Net-(P3-PadB5)"))
(pad B4 smd rect (at -4 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(pad S thru_hole rect (at -6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(pad B3 smd rect (at -5 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
(pad B2 smd rect (at -6 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
(pad B1 smd rect (at -7 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
(model /home/david/3d/470804001.stp
(offset (xyz -0.5 -5 3))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:Pulse_MagJack_JK0654219NL" (layer F.Cu) (tedit 5BF561A1) (tstamp 5BF66A32)
(at 66.415 111.6355)
(path /5CA09014/5CA2589B)
(fp_text reference P4 (at 4.826 9.398) (layer F.SilkS)
(module "Custom Parts:Molex_SATA_047080-4001" (layer F.Cu) (tedit 5BF5688A) (tstamp 5BF6681A)
(at 229.5 61.5 90)
(path /5C060E84/5C4A273B)
(fp_text reference P2 (at 6.7 -1.6 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value JK0654219NL (at 0 -9.525) (layer F.Fab)
(fp_text value SATA (at 0 5.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -17.0815 -8.4455) (end 6.858 -8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start 6.858 -8.4455) (end 6.858 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start 6.858 8.4455) (end -17.018 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 -8.4455) (end -19.7485 -8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 -8.4455) (end -26.162 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 8.4455) (end -19.812 8.4455) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 5.08) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 549 "Net-(C134-Pad1)"))
(pad 2 thru_hole circle (at 0 3.048) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 309 "/HDMI, GbE, USB/MX3-"))
(pad 3 thru_hole circle (at 0 1.016) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 310 "/HDMI, GbE, USB/MX3+"))
(pad 4 thru_hole circle (at 0 -1.016) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 312 "/HDMI, GbE, USB/MX2+"))
(pad 5 thru_hole circle (at 0 -3.048) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 311 "/HDMI, GbE, USB/MX2-"))
(pad 6 thru_hole circle (at 0 -5.08) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 548 "Net-(C133-Pad1)"))
(pad 7 thru_hole circle (at 2.54 6.096) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 547 "Net-(C135-Pad1)"))
(pad 8 thru_hole circle (at 2.54 4.064) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 307 "/HDMI, GbE, USB/MX4+"))
(pad 9 thru_hole circle (at 2.54 2.032) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 306 "/HDMI, GbE, USB/MX4-"))
(pad 10 thru_hole circle (at 2.54 -2.032) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 313 "/HDMI, GbE, USB/MX1-"))
(pad 11 thru_hole circle (at 2.54 -4.064) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 314 "/HDMI, GbE, USB/MX1+"))
(pad 12 thru_hole circle (at 2.54 -6.096) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 546 "Net-(C132-Pad1)"))
(pad 13 thru_hole circle (at 5.08 6.096) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(fp_line (start -9.3 9.2) (end -9.3 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -9.3 -0.8) (end -4.5 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 10) (end 8.3 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 -0.8) (end 4.4 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 6.6 10.8) (end 8.3 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start 8.3 10.8) (end 8.3 10) (layer F.SilkS) (width 0.15))
(fp_line (start 0.2 10.8) (end 5.6 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start 5.6 10.8) (end 6.6 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 10.8) (end -6.1 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 10.8) (end -9.3 10.8) (layer F.SilkS) (width 0.15))
(fp_line (start -9.3 10.8) (end -9.3 9.2) (layer F.SilkS) (width 0.15))
(fp_line (start -6.1 10.8) (end 0.3 10.8) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at 3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 14 thru_hole circle (at 5.08 3.556) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 198 "Net-(P4-Pad14)"))
(pad 15 thru_hole circle (at 5.08 -3.556) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(pad 2 smd rect (at 2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 422 "/PCIe + SATA/SATA1_A+"))
(pad 3 smd rect (at 1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 423 "/PCIe + SATA/SATA1_A-"))
(pad 4 smd rect (at 0 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 16 thru_hole circle (at 5.08 -6.096) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 189 "Net-(P4-Pad16)"))
(pad "" np_thru_hole circle (at -15.24 6.35) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -15.24 -6.35) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad S thru_hole circle (at -18.415 -8.0645) (size 2.6 2.6) (drill 1.57) (layers *.Cu *.Mask)
(pad 5 smd rect (at -1.27 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 424 "/PCIe + SATA/DCU1_RX1-"))
(pad 6 smd rect (at -2.54 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 425 "/PCIe + SATA/DCU1_RX1+"))
(pad 7 smd rect (at -3.81 0 90) (size 0.9 2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad S thru_hole circle (at -18.415 8.0645) (size 2.6 2.6) (drill 1.57) (layers *.Cu *.Mask)
(pad S thru_hole rect (at 6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(model /home/david/3d/JK0-0116NL_3D.STEP
(offset (xyz 6.5 0 6))
(pad S thru_hole rect (at -6.37 2.36 90) (size 2 3) (drill 1.5) (layers *.Cu *.Mask)
(net 24 GND))
(model /home/david/3d/470804001.stp
(offset (xyz -0.5 -5 3))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 90))
(rotate (xyz -90 0 0))
)
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF66AD3)
(at 135 30 180)
(path /61FAF948/64AB9BC6)
(fp_text reference J7 (at -13.5 0.5 270) (layer F.SilkS)
(module "Custom Parts:OSC_IDT_XU_5x3.2mm" (layer F.Cu) (tedit 5BF572F5) (tstamp 5BF66861)
(at 145.4 45.5 90)
(path /61FAF948/6249D25D)
(fp_text reference U26 (at 0.3 3.3 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT2 (at 0 -2 180) (layer F.Fab)
(fp_text value XL_XO_LVDS (at 0 -2.7 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(fp_line (start -1.3 1.9) (end -1.6 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 2.2) (end -1 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1 2.2) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8 1.6) (end -2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 1.6) (end -2.5 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 -1.6) (end -1.8 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.6 -1.6) (end 0.7 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -1.6) (end -0.6 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.6 1.6) (end -0.7 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.7 1.6) (end 0.6 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 1.6) (end 1.9 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 1.6) (end 1.8 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 1.8 -1.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 579 "Net-(U26-Pad1)"))
(pad 2 smd rect (at 0 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 580 "Net-(U26-Pad2)"))
(pad 3 smd rect (at 1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at 1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 581 "/FPGA IO/CLK100+"))
(pad 5 smd rect (at 0 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 582 "/FPGA IO/CLK100-"))
(pad 6 smd rect (at -1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 12 +3V3))
)
(module "Custom Parts:OSC_IDT_XU_5x3.2mm" (layer F.Cu) (tedit 5BF572F5) (tstamp 5BF668A6)
(at 124.3 101.9 90)
(path /5C060E84/5C744CC2)
(fp_text reference U14 (at 0.3 3.3 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(fp_text value " XUL535150.000JS6I8" (at 0 -2.7 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 521 "/FPGA IO/EXT2_0+"))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 522 "/FPGA IO/EXT2_0-"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 523 "/FPGA IO/EXT2_1+"))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 524 "/FPGA IO/EXT2_1-"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 525 "/FPGA IO/EXT2_2+"))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 526 "/FPGA IO/EXT2_2-"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 527 "/FPGA IO/EXT2_3+"))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 528 "/FPGA IO/EXT2_3-"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 529 "/FPGA IO/EXT2_4+"))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 530 "/FPGA IO/EXT2_4-"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 531 "/FPGA IO/EXT2_5+"))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 532 "/FPGA IO/EXT2_5-"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 533 "/FPGA IO/EXT2_6+"))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 534 "/FPGA IO/EXT2_6-"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 535 "/FPGA IO/EXT2_7+"))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 536 "/FPGA IO/EXT2_7-"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 537 "/FPGA IO/EXT2_8+"))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 538 "/FPGA IO/EXT2_8-"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 539 "/FPGA IO/EXT2_9+"))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 540 "/FPGA IO/EXT2_9-"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 541 "/FPGA IO/EXT2_10+"))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 542 "/FPGA IO/EXT2_10-"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 543 "/FPGA IO/EXT2_11+"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 544 "/FPGA IO/EXT2_11-"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 545 "Net-(J7-Pad38)"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(fp_line (start -1.3 1.9) (end -1.6 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 2.2) (end -1 2.2) (layer F.SilkS) (width 0.15))
(fp_line (start -1 2.2) (end -1.3 1.9) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8 1.6) (end -2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 1.6) (end -2.5 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5 -1.6) (end -1.8 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.6 -1.6) (end 0.7 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -1.6) (end -0.6 -1.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.6 1.6) (end -0.7 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 0.7 1.6) (end 0.6 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 2.5 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 1.6) (end 1.9 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 1.6) (end 1.8 1.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 -1.6) (end 1.8 -1.6) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 578 "Net-(U14-Pad1)"))
(pad 2 smd rect (at 0 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 577 "Net-(U14-Pad2)"))
(pad 3 smd rect (at 1.27 1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 4 smd rect (at 1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 120 "/PCIe + SATA/CLK150M+"))
(pad 5 smd rect (at 0 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 115 "/PCIe + SATA/CLK150M-"))
(pad 6 smd rect (at -1.27 -1.1049 90) (size 0.89 1.29) (layers F.Cu F.Paste F.Mask)
(net 416 "Net-(C111-Pad1)"))
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF66BA8)
(at 106 30 180)
(path /61FAF948/635A137F)
(fp_text reference J6 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT1 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(module "Custom Parts:PCIe_EDGE_x4" locked (layer F.Cu) (tedit 5BF55C2C) (tstamp 5BF6693F)
(at 92.9 131.4)
(path /5C060E84/5C060EE2)
(fp_text reference P3 (at 0 -7.35) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(fp_text value PCIe_x4_EDGE (at 0 -5.08) (layer Edge.Cuts)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 520 "/FPGA IO/EXT1_0+"))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 519 "/FPGA IO/EXT1_0-"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 518 "/FPGA IO/EXT1_1+"))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 517 "/FPGA IO/EXT1_1-"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(fp_arc (start 4.5 -3.95) (end 3.55 -3.95) (angle 180) (layer Edge.Cuts) (width 0.15))
(fp_line (start 5.45 -3.95) (end 5.45 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.55 3.5) (end -6.9 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.55 -3.95) (end 3.55 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 5.45 3.5) (end 26.65 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 3.5) (end 26.65 -3.2) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 3.5) (end -7.65 -2.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 3.5) (end -6.9 3.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 3.7 -107.65) (end 105.4 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_arc (start -9.475 -7.425) (end -11.3 -7.425) (angle 180) (layer Edge.Cuts) (width 0.15))
(fp_line (start -7.65 -7.425) (end -7.65 -2.47) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -1) (end -11.9 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -2.8) (end -11.3 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -7.2) (end -11.3 -2.8) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.3 -7.45) (end -11.3 -7.2) (layer Edge.Cuts) (width 0.15))
(fp_line (start -11.9 -1) (end -19.3 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -107.65) (end 3.7 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -1) (end -52.65 -106.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -37.65 -1) (end -52.65 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -37.65 -9.25) (end -37.65 -1) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -9.25) (end -37.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start -19.3 -1) (end -19.3 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -107.65) (end -19.3 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start -52.65 -106.65) (end -52.65 -107.65) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 -9.25) (end 76.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 26.65 -3.2) (end 26.65 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 76.6 -9.25) (end 79.4 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.4 -9.25) (end 79.4 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 92.1 -1.88) (end 92.1 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.9 0.55) (end 90.71 0.55) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.4 -4.45) (end 79.4 0.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start 88.15 -9.25) (end 105.4 -9.25) (layer Edge.Cuts) (width 0.15))
(fp_line (start 86.4 -6.2) (end 86.4 -7.5) (layer Edge.Cuts) (width 0.15))
(fp_line (start 92.1 -4.45) (end 88.15 -4.45) (layer Edge.Cuts) (width 0.15))
(fp_line (start 79.9 0.55) (end 79.4 0.05) (layer Edge.Cuts) (width 0.15))
(fp_line (start 90.7 0.55) (end 92.1 -1.88) (layer Edge.Cuts) (width 0.15))
(fp_arc (start 88.15 -7.5) (end 88.15 -9.25) (angle -90) (layer Edge.Cuts) (width 0.15))
(fp_arc (start 88.15 -6.2) (end 86.4 -6.2) (angle -90) (layer Edge.Cuts) (width 0.15))
(pad M thru_hole circle (at -45.1 -91.2) (size 5 5) (drill 3.18) (layers *.Cu *.Mask))
(pad M thru_hole circle (at -45.15 -5.85) (size 5 5) (drill 3.18) (layers *.Cu *.Mask))
(pad A32 smd rect (at 26 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 576 "Net-(P3-PadA32)"))
(pad A31 smd rect (at 25 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 516 "/FPGA IO/EXT1_2+"))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 515 "/FPGA IO/EXT1_2-"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A30 smd rect (at 24 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 575 "Net-(P3-PadA30)"))
(pad A29 smd rect (at 23 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 574 "Net-(P3-PadA29)"))
(pad A28 smd rect (at 22 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 514 "/FPGA IO/EXT1_3+"))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 513 "/FPGA IO/EXT1_3-"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A27 smd rect (at 21 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 512 "/FPGA IO/EXT1_4+"))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 511 "/FPGA IO/EXT1_4-"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A26 smd rect (at 20 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 573 "Net-(P3-PadA26)"))
(pad A25 smd rect (at 19 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 572 "Net-(P3-PadA25)"))
(pad A24 smd rect (at 18 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 510 "/FPGA IO/EXT1_5+"))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 509 "/FPGA IO/EXT1_5-"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A23 smd rect (at 17 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 508 "/FPGA IO/EXT1_6+"))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 507 "/FPGA IO/EXT1_6-"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A22 smd rect (at 16 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 433 "/PCIe + SATA/PCIe_HSI1-"))
(pad A21 smd rect (at 15 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 432 "/PCIe + SATA/PCIe_HSI1+"))
(pad A20 smd rect (at 14 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 506 "/FPGA IO/EXT1_7+"))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 505 "/FPGA IO/EXT1_7-"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A19 smd rect (at 13 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 571 "Net-(P3-PadA19)"))
(pad A18 smd rect (at 12 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 504 "/FPGA IO/EXT1_8+"))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 503 "/FPGA IO/EXT1_8-"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A17 smd rect (at 11 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 431 "/PCIe + SATA/PCIe_HSI0-"))
(pad A16 smd rect (at 10 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 430 "/PCIe + SATA/PCIe_HSI0+"))
(pad A15 smd rect (at 9 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 502 "/FPGA IO/EXT1_9+"))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 501 "/FPGA IO/EXT1_9-"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A14 smd rect (at 8 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 125 "/PCIe + SATA/PCIe_REFCLK-"))
(pad A13 smd rect (at 7 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 124 "/PCIe + SATA/PCIe_REFCLK+"))
(pad A12 smd rect (at 6 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 500 "/FPGA IO/EXT1_10+"))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 499 "/FPGA IO/EXT1_10-"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A11 smd rect (at 3 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 129 "Net-(P3-PadA11)"))
(pad A10 smd rect (at 2 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 570 "Net-(P3-PadA10)"))
(pad A9 smd rect (at 1 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 569 "Net-(P3-PadA9)"))
(pad A8 smd rect (at 0 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 568 "Net-(P3-PadA8)"))
(pad A7 smd rect (at -1 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 567 "Net-(P3-PadA7)"))
(pad A6 smd rect (at -2 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 566 "Net-(P3-PadA6)"))
(pad A5 smd rect (at -3 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 565 "Net-(P3-PadA5)"))
(pad A4 smd rect (at -4 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 24 GND))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 498 "/FPGA IO/EXT1_11+"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 497 "/FPGA IO/EXT1_11-"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 496 "Net-(J6-Pad38)"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF675A7)
(at 164 30 180)
(path /61FAF948/65FA91E0)
(fp_text reference J8 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT3 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 471 "/FPGA IO/EXT3_0+"))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 472 "/FPGA IO/EXT3_0-"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad A3 smd rect (at -5 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 126 PCIe_12V))
(pad A2 smd rect (at -6 0) (size 0.75 4.2) (layers B.Cu B.Paste B.Mask)
(net 126 PCIe_12V))
(pad A1 smd rect (at -7 -0.5) (size 0.75 3.2) (layers B.Cu B.Paste B.Mask)
(net 564 "/PCIe + SATA/~PRSNT1"))
(pad B32 smd rect (at 26 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 473 "/FPGA IO/EXT3_1+"))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 474 "/FPGA IO/EXT3_1-"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B31 smd rect (at 25 -0.5) (size 0.75 3.2) (layers F.Cu F.Paste F.Mask)
(net 563 "/PCIe + SATA/~PRSNT2~_X4"))
(pad B30 smd rect (at 24 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 562 "Net-(P3-PadB30)"))
(pad B29 smd rect (at 23 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 475 "/FPGA IO/EXT3_2+"))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 476 "/FPGA IO/EXT3_2-"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B28 smd rect (at 22 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 561 "Net-(P3-PadB28)"))
(pad B27 smd rect (at 21 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 560 "Net-(P3-PadB27)"))
(pad B26 smd rect (at 20 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 477 "/FPGA IO/EXT3_3+"))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 478 "/FPGA IO/EXT3_3-"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B25 smd rect (at 19 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 479 "/FPGA IO/EXT3_4+"))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 480 "/FPGA IO/EXT3_4-"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B24 smd rect (at 18 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 559 "Net-(P3-PadB24)"))
(pad B23 smd rect (at 17 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 558 "Net-(P3-PadB23)"))
(pad B22 smd rect (at 16 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 481 "/FPGA IO/EXT3_5+"))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 482 "/FPGA IO/EXT3_5-"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B21 smd rect (at 15 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 483 "/FPGA IO/EXT3_6+"))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 484 "/FPGA IO/EXT3_6-"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B20 smd rect (at 14 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 437 "/PCIe + SATA/DCU0_RX1-"))
(pad B19 smd rect (at 13 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 436 "/PCIe + SATA/DCU0_RX1+"))
(pad B18 smd rect (at 12 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 485 "/FPGA IO/EXT3_7+"))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 486 "/FPGA IO/EXT3_7-"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B17 smd rect (at 11 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 557 "/PCIe + SATA/~PRSNT2~_X1"))
(pad B16 smd rect (at 10 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 487 "/FPGA IO/EXT3_8+"))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 488 "/FPGA IO/EXT3_8-"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B15 smd rect (at 9 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 435 "/PCIe + SATA/DCU0_RX0-"))
(pad B14 smd rect (at 8 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 434 "/PCIe + SATA/DCU0_RX0+"))
(pad B13 smd rect (at 7 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 489 "/FPGA IO/EXT3_9+"))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 490 "/FPGA IO/EXT3_9-"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B12 smd rect (at 6 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 556 "Net-(P3-PadB12)"))
(pad B11 smd rect (at 3 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 555 PCIe_~WAKE))
(pad B10 smd rect (at 2 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 554 "Net-(P3-PadB10)"))
(pad B9 smd rect (at 1 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 553 "Net-(P3-PadB9)"))
(pad B8 smd rect (at 0 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 552 "Net-(P3-PadB8)"))
(pad B7 smd rect (at -1 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 491 "/FPGA IO/EXT3_10+"))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 492 "/FPGA IO/EXT3_10-"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad B6 smd rect (at -2 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 551 "Net-(P3-PadB6)"))
(pad B5 smd rect (at -3 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 550 "Net-(P3-PadB5)"))
(pad B4 smd rect (at -4 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 493 "/FPGA IO/EXT3_11+"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 494 "/FPGA IO/EXT3_11-"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 495 "Net-(J8-Pad38)"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 105 "/FPGA IO/VCCIO7"))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad B3 smd rect (at -5 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
(pad B2 smd rect (at -6 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
(pad B1 smd rect (at -7 0) (size 0.75 4.2) (layers F.Cu F.Paste F.Mask)
(net 126 PCIe_12V))
)
(module "Custom Parts:TE_FPC_40pin_p0.5mm_4-1734839-0" (layer F.Cu) (tedit 5BF58209) (tstamp 5BF676D0)
(at 77 30 180)
(path /61FAF948/62664D22)
(fp_text reference J5 (at -13.5 0.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EXT0 (at 0 -2 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75 180) (layer F.SilkS)
(module "Custom Parts:Pulse_MagJack_JK0654219NL" (layer F.Cu) (tedit 5BF561A1) (tstamp 5BF66A32)
(at 66.415 111.6355)
(path /5CA09014/5CA2589B)
(fp_text reference P4 (at 4.826 9.398) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 1 (at -10.5 -0.75 180) (layer F.SilkS)
(fp_text value JK0654219NL (at 0 -9.525) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 2 smd rect (at -9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 3 smd rect (at -8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 470 "/FPGA IO/EXT0_0+"))
(pad 4 smd rect (at -8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 469 "/FPGA IO/EXT0_0-"))
(pad 5 smd rect (at -7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 6 smd rect (at -7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 468 "/FPGA IO/EXT0_1+"))
(pad 7 smd rect (at -6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 467 "/FPGA IO/EXT0_1-"))
(pad 8 smd rect (at -6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 9 smd rect (at -5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 466 "/FPGA IO/EXT0_2+"))
(pad 10 smd rect (at -5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 465 "/FPGA IO/EXT0_2-"))
(pad 11 smd rect (at -4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 12 smd rect (at -4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 464 "/FPGA IO/EXT0_3+"))
(pad 13 smd rect (at -3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 463 "/FPGA IO/EXT0_3-"))
(pad 14 smd rect (at -3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 15 smd rect (at -2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 462 "/FPGA IO/EXT0_4+"))
(pad 16 smd rect (at -2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 461 "/FPGA IO/EXT0_4-"))
(pad 17 smd rect (at -1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 18 smd rect (at -1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 460 "/FPGA IO/EXT0_5+"))
(pad 19 smd rect (at -0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 459 "/FPGA IO/EXT0_5-"))
(pad 20 smd rect (at -0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 21 smd rect (at 0.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 458 "/FPGA IO/EXT0_6+"))
(pad 22 smd rect (at 0.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 457 "/FPGA IO/EXT0_6-"))
(pad 23 smd rect (at 1.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 24 GND))
(pad 24 smd rect (at 1.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 456 "/FPGA IO/EXT0_7+"))
(pad 25 smd rect (at 2.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 455 "/FPGA IO/EXT0_7-"))
(pad 26 smd rect (at 2.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(fp_line (start -17.0815 -8.4455) (end 6.858 -8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start 6.858 -8.4455) (end 6.858 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start 6.858 8.4455) (end -17.018 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 -8.4455) (end -19.7485 -8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 -8.4455) (end -26.162 8.4455) (layer F.SilkS) (width 0.15))
(fp_line (start -26.162 8.4455) (end -19.812 8.4455) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 5.08) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 549 "Net-(C134-Pad1)"))
(pad 2 thru_hole circle (at 0 3.048) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 309 "/HDMI, GbE, USB/MX3-"))
(pad 3 thru_hole circle (at 0 1.016) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 310 "/HDMI, GbE, USB/MX3+"))
(pad 4 thru_hole circle (at 0 -1.016) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 312 "/HDMI, GbE, USB/MX2+"))
(pad 5 thru_hole circle (at 0 -3.048) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 311 "/HDMI, GbE, USB/MX2-"))
(pad 6 thru_hole circle (at 0 -5.08) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 548 "Net-(C133-Pad1)"))
(pad 7 thru_hole circle (at 2.54 6.096) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 547 "Net-(C135-Pad1)"))
(pad 8 thru_hole circle (at 2.54 4.064) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 307 "/HDMI, GbE, USB/MX4+"))
(pad 9 thru_hole circle (at 2.54 2.032) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 306 "/HDMI, GbE, USB/MX4-"))
(pad 10 thru_hole circle (at 2.54 -2.032) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 313 "/HDMI, GbE, USB/MX1-"))
(pad 11 thru_hole circle (at 2.54 -4.064) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 314 "/HDMI, GbE, USB/MX1+"))
(pad 12 thru_hole circle (at 2.54 -6.096) (size 1.524 1.524) (drill 0.889) (layers *.Cu *.Mask)
(net 546 "Net-(C132-Pad1)"))
(pad 13 thru_hole circle (at 5.08 6.096) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 24 GND))
(pad 27 smd rect (at 3.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 454 "/FPGA IO/EXT0_8+"))
(pad 28 smd rect (at 3.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 453 "/FPGA IO/EXT0_8-"))
(pad 29 smd rect (at 4.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad 14 thru_hole circle (at 5.08 3.556) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 198 "Net-(P4-Pad14)"))
(pad 15 thru_hole circle (at 5.08 -3.556) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 24 GND))
(pad 30 smd rect (at 4.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 452 "/FPGA IO/EXT0_9+"))
(pad 31 smd rect (at 5.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 451 "/FPGA IO/EXT0_9-"))
(pad 32 smd rect (at 5.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad 16 thru_hole circle (at 5.08 -6.096) (size 1.8 1.8) (drill 1.03) (layers *.Cu *.Mask)
(net 189 "Net-(P4-Pad16)"))
(pad "" np_thru_hole circle (at -15.24 6.35) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -15.24 -6.35) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad S thru_hole circle (at -18.415 -8.0645) (size 2.6 2.6) (drill 1.57) (layers *.Cu *.Mask)
(net 24 GND))
(pad 33 smd rect (at 6.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 450 "/FPGA IO/EXT0_10+"))
(pad 34 smd rect (at 6.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 449 "/FPGA IO/EXT0_10-"))
(pad 35 smd rect (at 7.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(pad S thru_hole circle (at -18.415 8.0645) (size 2.6 2.6) (drill 1.57) (layers *.Cu *.Mask)
(net 24 GND))
(pad 36 smd rect (at 7.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 448 "/FPGA IO/EXT0_11+"))
(pad 37 smd rect (at 8.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 447 "/FPGA IO/EXT0_11-"))
(pad 38 smd rect (at 8.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 446 "Net-(J5-Pad38)"))
(pad 39 smd rect (at 9.25 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad 40 smd rect (at 9.75 0 180) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask)
(net 119 "/FPGA IO/VCCIO6"))
(pad "" smd rect (at 11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -11.42 1.7 180) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(model /home/david/3d/JK0-0116NL_3D.STEP
(offset (xyz 6.5 0 6))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 90))
)
)
(module "Custom Parts:TI_VSON-HR_1.5x2mm_p0.5mm" (layer F.Cu) (tedit 5BF57A12) (tstamp 5BF6774E)
@ -15610,10 +15670,10 @@
(net 196 +1V2))
(pad 1 smd rect (at -1.655 0 270) (size 1.2 4.7) (layers F.Cu F.Paste F.Mask)
(net 231 "Net-(L1-Pad1)"))
(model ${KISYS3DMOD}/Inductor_SMD.3dshapes/L_Coilcraft_XAL5030.wrl
(model /home/david/3d/Coilcraft-XAL5030.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz -90 0 0))
)
)
@ -15650,10 +15710,10 @@
(net 116 +1V8))
(pad 1 smd rect (at -1.35 0 180) (size 1.5 1.2) (layers F.Cu F.Paste F.Mask)
(net 415 "Net-(L6-Pad1)"))
(model ${KISYS3DMOD}/Inductor_SMD.3dshapes/L_Vishay_IHLP-1212.wrl
(at (xyz 0 0 0))
(model "/home/david/3d/User Library-IHLP1212.step"
(offset (xyz 1.75 -1.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz 0 0 180))
)
)
@ -15695,6 +15755,11 @@
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model "/home/david/3d/User Library-IHLP1212.step"
(offset (xyz 1.75 -1.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 180))
)
)
(module Inductor_SMD:L_Vishay_IHLP-1212 (layer F.Cu) (tedit 5990349D) (tstamp 5BF67DFA)
@ -15730,10 +15795,10 @@
(net 117 +2V5))
(pad 1 smd rect (at -1.35 0 180) (size 1.5 1.2) (layers F.Cu F.Paste F.Mask)
(net 413 "Net-(L5-Pad1)"))
(model ${KISYS3DMOD}/Inductor_SMD.3dshapes/L_Vishay_IHLP-1212.wrl
(at (xyz 0 0 0))
(model "/home/david/3d/User Library-IHLP1212.step"
(offset (xyz 1.75 -1.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz 0 0 180))
)
)
@ -15770,10 +15835,10 @@
(net 12 +3V3))
(pad 1 smd rect (at -1.35 0 180) (size 1.5 1.2) (layers F.Cu F.Paste F.Mask)
(net 412 "Net-(L4-Pad1)"))
(model ${KISYS3DMOD}/Inductor_SMD.3dshapes/L_Vishay_IHLP-1212.wrl
(at (xyz 0 0 0))
(model "/home/david/3d/User Library-IHLP1212.step"
(offset (xyz 1.75 -1.5 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
(rotate (xyz 0 0 180))
)
)
@ -17431,7 +17496,7 @@
(net 265 DVI_DE))
(pad 1 smd rect (at -5.7 -3.75 270) (size 1.5 0.3) (layers F.Cu F.Paste F.Mask)
(net 264 "/HDMI, GbE, USB/DVI_DVDD"))
(model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-64_10x10mm_Pitch0.5mm_EP8x8mm.wrl
(model ${KISYS3DMOD}/Package_QFP.3dshapes/HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
@ -17736,7 +17801,7 @@
(net 30 "/FPGA IO/FLASH_D1"))
(pad 1 smd rect (at -3.7 -1.905) (size 1.75 0.55) (layers F.Cu F.Paste F.Mask)
(net 149 "/FPGA IO/FLASH_~CS"))
(model ${KISYS3DMOD}/Package_SO.3dshapes/SO-8_5.3x6.2mm_P1.27mm.wrl
(model ${KISYS3DMOD}/Package_SO.3dshapes/SOIJ-8_5.3x5.3mm_P1.27mm.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))

111
hardware/lib/parts.pretty/TE_FPC_40pin_p0.5mm_4-1734839-0.kicad_mod
Unescape View File

@ -1,64 +1,69 @@
(module TE_FPC_40pin_p0.5mm_4-1734839-0 (layer F.Cu) (tedit 5BF58209)
(fp_text reference REF** (at -13.5 0.5 90) (layer F.SilkS)
(fp_text reference J8 (at -13.5 0.5 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TE_FPC_40pin_p0.5mm_4-1734839-0 (at 0 -2) (layer F.Fab)
(fp_text value EXT3 (at 0 -2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -10.5 -0.75) (layer F.SilkS)
(fp_text user 40 (at 11 -0.75) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user 40 (at 11 -0.75) (layer F.SilkS)
(fp_text user 1 (at -10.5 -0.75) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" smd rect (at -11.42 1.7) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 39 smd rect (at 9.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 8.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 8.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 7.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 7.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at 6.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 6.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at 5.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at 5.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at 4.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at 4.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 3.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 3.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 2.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 2.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 1.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 1.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 0.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 0.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at -0.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at -0.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at -1.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at -1.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at -2.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at -2.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at -3.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -3.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -4.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -4.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -5.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -5.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -6.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -6.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -7.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -7.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -8.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -8.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -9.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(fp_line (start 13.14 3.85) (end 13.14 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 13.14 3.25) (end 12.98 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.71 3.25) (end 13.03 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.86) (end -13.02 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start -13.02 3.25) (end -12.66 3.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.91 3.85) (end -13.02 3.86) (layer F.SilkS) (width 0.15))
(fp_line (start 11.32 3.85) (end 13.14 3.85) (layer F.SilkS) (width 0.15))
(fp_line (start 11.39 3.85) (end 10.9 3.85) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -9.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -9.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -8.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -8.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -7.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -7.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -6.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -6.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -5.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -5.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -4.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -4.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -3.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at -3.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at -2.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at -2.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at -1.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at -1.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at -0.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at -0.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 0.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 0.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 1.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 1.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 2.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 2.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 3.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 3.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at 4.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at 4.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at 5.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at 5.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 6.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at 6.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 7.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 7.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 8.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 8.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 39 smd rect (at 9.25 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad 40 smd rect (at 9.75 0) (size 0.3 1.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at 11.42 1.7) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(pad "" smd rect (at -11.42 1.7) (size 2.3 3.1) (layers F.Cu F.Paste F.Mask))
(model /home/david/3d/c-4-1734839-0-c-3d.stp
(offset (xyz 0 -5 1))
(scale (xyz 1 1 1))
(rotate (xyz -90 0 0))
)
)

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