ecp5_mainboard/power: Add 1.35V DDR3 and 1.2V FPGA core regulators

Signed-off-by: David Shah <davey1576@gmail.com>
master
David Shah 6 years ago
parent 80f8119591
commit 9198ed3c29

@ -244,6 +244,39 @@ X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# eco_power:LM21212-2
#
DEF eco_power:LM21212-2 U 0 40 Y Y 1 F N
F0 "U" -500 -700 50 H V L CNN
F1 "eco_power:LM21212-2" 0 0 50 H V C CNN
F2 "" 0 -550 50 H I C CNN
F3 "" 0 -550 50 H I C CNN
DRAW
S -500 650 500 -650 0 1 0 f
X FAdj 1 -700 -50 200 R 50 50 1 1 I
X PGND 10 -700 -550 200 R 50 50 1 1 I
X SW 11 700 550 200 L 50 50 1 1 O
X SW 12 700 450 200 L 50 50 1 1 O
X SW 13 700 350 200 L 50 50 1 1 O
X SW 14 700 250 200 L 50 50 1 1 O
X SW 15 700 150 200 L 50 50 1 1 O
X SW 16 700 50 200 L 50 50 1 1 O
X PGOOD 17 700 -350 200 L 50 50 1 1 I
X COMP 18 700 -250 200 L 50 50 1 1 I
X FB 19 700 -150 200 L 50 50 1 1 I
X SS/TRK 2 -700 -150 200 R 50 50 1 1 I
X AGND 20 700 -550 200 L 50 50 1 1 W
X EP 21 0 -850 200 U 50 50 1 1 P
X EN 3 -700 50 200 R 50 50 1 1 I
X AVin 4 -700 550 200 R 50 50 1 1 W
X PVin 5 -700 450 200 R 50 50 1 1 W
X PVin 6 -700 350 200 R 50 50 1 1 W
X PVin 7 -700 250 200 R 50 50 1 1 W
X PGND 8 -700 -350 200 R 50 50 1 1 I
X PGND 9 -700 -450 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# eco_power:TPS25944A # eco_power:TPS25944A
# #
DEF eco_power:TPS25944A U 0 40 Y Y 1 F N DEF eco_power:TPS25944A U 0 40 Y Y 1 F N
@ -373,6 +406,36 @@ X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# power:+1V2
#
DEF power:+1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power:+1V2" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power:+1V35
#
DEF power:+1V35 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power:+1V35" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V35 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power:+1V8 # power:+1V8
# #
DEF power:+1V8 #PWR 0 0 Y Y 1 F P DEF power:+1V8 #PWR 0 0 Y Y 1 F P

File diff suppressed because it is too large Load Diff

@ -1,5 +1,9 @@
EESchema-DOCLIB Version 2.0 EESchema-DOCLIB Version 2.0
# #
$CMP LM21212-2
D 12A High Efficiency Synchronous Buck
$ENDCMP
#
$CMP TPS25944A $CMP TPS25944A
D 2.7V-18V, 5A eFuse Power Mux D 2.7V-18V, 5A eFuse Power Mux
K efuse power mux powerpath fet K efuse power mux powerpath fet

@ -1,6 +1,39 @@
EESchema-LIBRARY Version 2.4 EESchema-LIBRARY Version 2.4
#encoding utf-8 #encoding utf-8
# #
# LM21212-2
#
DEF LM21212-2 U 0 40 Y Y 1 F N
F0 "U" -500 -700 50 H V L CNN
F1 "LM21212-2" 0 0 50 H V C CNN
F2 "" 0 -550 50 H I C CNN
F3 "" 0 -550 50 H I C CNN
DRAW
S -500 650 500 -650 0 1 0 f
X FAdj 1 -700 -50 200 R 50 50 1 1 I
X PGND 10 -700 -550 200 R 50 50 1 1 I
X SW 11 700 550 200 L 50 50 1 1 O
X SW 12 700 450 200 L 50 50 1 1 O
X SW 13 700 350 200 L 50 50 1 1 O
X SW 14 700 250 200 L 50 50 1 1 O
X SW 15 700 150 200 L 50 50 1 1 O
X SW 16 700 50 200 L 50 50 1 1 O
X PGOOD 17 700 -350 200 L 50 50 1 1 I
X COMP 18 700 -250 200 L 50 50 1 1 I
X FB 19 700 -150 200 L 50 50 1 1 I
X SS/TRK 2 -700 -150 200 R 50 50 1 1 I
X AGND 20 700 -550 200 L 50 50 1 1 W
X EP 21 0 -850 200 U 50 50 1 1 P
X EN 3 -700 50 200 R 50 50 1 1 I
X AVin 4 -700 550 200 R 50 50 1 1 W
X PVin 5 -700 450 200 R 50 50 1 1 W
X PVin 6 -700 350 200 R 50 50 1 1 W
X PVin 7 -700 250 200 R 50 50 1 1 W
X PGND 8 -700 -350 200 R 50 50 1 1 I
X PGND 9 -700 -450 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# TPS25944A # TPS25944A
# #
DEF TPS25944A U 0 40 Y Y 1 F N DEF TPS25944A U 0 40 Y Y 1 F N

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