David Shah
6 years ago
parent
cee0607ba2
commit
bbf899e51d
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# This file is Copyright (c) 2019 David Shah <dave@ds0.me>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("B29"), IOStandard("LVDS")),
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("clk12", 0, Pins("B3"), IOStandard("LVCMOS33")),
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("clkref", 0, Pins("E17"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("Y32"), IOStandard("SSTL135_I")),
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("user_btn", 1, Pins("W31"), IOStandard("SSTL135_I")),
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("user_btn", 2, Pins("AD30"), IOStandard("SSTL135_I")),
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("user_btn", 3, Pins("AD29"), IOStandard("SSTL135_I")),
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("user_dip", 0, Pins("AE31"), IOStandard("SSTL135_I")),
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("user_dip", 1, Pins("AE32"), IOStandard("SSTL135_I")),
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("user_dip", 2, Pins("AD32"), IOStandard("SSTL135_I")),
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("user_dip", 3, Pins("AC32"), IOStandard("SSTL135_I")),
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("user_dip", 4, Pins("AB32"), IOStandard("SSTL135_I")),
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("user_dip", 5, Pins("AB31"), IOStandard("SSTL135_I")),
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("user_dip", 6, Pins("AC31"), IOStandard("SSTL135_I")),
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("user_dip", 7, Pins("AC30"), IOStandard("SSTL135_I")),
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("user_led", 0, Pins("C26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D26"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A28"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("A29"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("A30"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("AK29"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("AH32"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("AH30"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("AH28"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("AG30"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("AG29"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("AK30"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("rx", Pins("AM28"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("AL28"), IOStandard("LVCMOS33")),
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),
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("ftdi", 0,
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Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")),
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Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")),
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Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")),
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Subsignal("rd_n", Pins("AL32"), IOStandard("LVCMOS33")),
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Subsignal("wr_n", Pins("AG28"), IOStandard("LVCMOS33")),
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Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"E30 F28 C32 E29 F32 D30 E32 D29",
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"D32 C31 H32 F31 F29 B32 D31"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("H31 H30 J30"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("K30"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("K31"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("J32"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("K29"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("R26 L27 Y27 U31"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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" V26 R27 V27 T26 U28 T27 T29 U26",
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" P27 K28 P26 L26 K27 N26 L29 K26",
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"AC27 W28 AC26 Y26 AB26 W29 AD26 Y28",
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" T32 U32 P31 V32 P32 W32 N32 U30"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("R29 N30 AB28 R32"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("L31"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("K32"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("J29"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("L32"), IOStandard("SSTL135_I")),
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Subsignal("vtt_en", Pins("E25"), IOStandard("LVCMOS33")),
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Misc("SLEWRATE=FAST"),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("A15")),
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Subsignal("rx", Pins("C17")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("D16")),
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Subsignal("mdio", Pins("F17")),
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Subsignal("mdc", Pins("B17")),
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Subsignal("rx_ctl", Pins("A16")),
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Subsignal("rx_data", Pins("C16 B16 B14 F16")),
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Subsignal("tx_ctl", Pins("D15")),
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Subsignal("tx_data", Pins("A14 F15 C15 C14")),
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IOStandard("LVCMOS33")
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),
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("clkgen", 0,
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Subsignal("sda", Pins("C22")),
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Subsignal("scl", Pins("A22")),
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Subsignal("sd_oe", Pins("A2")),
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IOStandard("LVCMOS33")
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),
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("pcie_x2", 0,
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Subsignal("clk_p", Pins("AM14")),
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Subsignal("clk_n", Pins("AM15")),
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Subsignal("rx_p", Pins("AM8 AK12")),
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Subsignal("rx_n", Pins("AM9 AK13")),
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Subsignal("tx_p", Pins("AK9 AM11")),
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Subsignal("tx_n", Pins("AK10 AM12")),
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Subsignal("perst", Pins("D22"), IOStandard("LVCMOS33")),
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Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")),
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),
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("m2", 0,
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Subsignal("clk_p", Pins("AM23")),
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Subsignal("clk_n", Pins("AM24")),
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Subsignal("rx_p", Pins("AM17 AK21")),
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Subsignal("rx_n", Pins("AM18 AK22")),
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Subsignal("tx_p", Pins("AK18 AM20")),
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Subsignal("tx_n", Pins("AK19 AM21")),
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Subsignal("clksel", Pins("N3"), IOStandard("LVCMOS33")),
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Subsignal("sdio_clk", Pins("L4"), IOStandard("LVCMOS33")),
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Subsignal("sdio_cmd", Pins("K4"), IOStandard("LVCMOS33")),
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Subsignal("sdio_dq", Pins("L7 N4 L6 N6"), IOStandard("LVCMOS33")),
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Subsignal("uart_tx", Pins("P6"), IOStandard("LVCMOS33")),
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Subsignal("uart_rx", Pins("K5"), IOStandard("LVCMOS33")),
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Subsignal("uart_rts_n", Pins("N7"), IOStandard("LVCMOS33")),
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Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs)
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
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except ConstraintError:
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pass
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def create_programmer(self, with_ispclock=True):
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_xcf_ispclock = """
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<Device>
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<SelectedProg value="FALSE"/>
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<Pos>2</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ispCLOCK</Family>
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<Name>ispPAC-CLK5406D</Name>
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<IDCode>0x00191043</IDCode>
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<Operation>Erase,Program,Verify</Operation>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Device>
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"""
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.4.1">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ECP5UM5G</Family>
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<Name>LFE5UM5G-45F</Name>
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<IDCode>0x81112043</IDCode>
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<File>{{bitstream_file}}</File>
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<Operation>Fast Program</Operation>
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</Device>{ispclock}
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
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</CableOptions>
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</ispXCF>
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""".format(ispclock=_xcf_ispclock if with_ispclock else "")
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return LatticeProgrammer(_xcf_template)
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