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hardware/mainboard: Silk fixes

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Signed-off-by: David Shah <dave@ds0.me>
master
David Shah 6 years ago
parent d0b2161939
commit caafcb5250
2 changed files with 190 additions and 127 deletions
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232
hardware/ecp5_mainboard/ecp5_mainboard.kicad_pcb
Unescape View File

@ -2,7 +2,7 @@
(general
(thickness 1.6)
(drawings 174)
(drawings 180)
(tracks 47469)
(zones 0)
(modules 510)
@ -11,7 +11,7 @@
(page A4)
(layers
(0 F.Cu signal hide)
(0 F.Cu signal)
(1 In1.Cu signal)
(2 In2.Cu signal)
(3 In3.Cu signal)
@ -49,7 +49,7 @@
(user_trace_width 0.5)
(user_trace_width 0.8)
(user_trace_width 1)
(trace_clearance 0.0889)
(trace_clearance 0.0762)
(zone_clearance 0.15)
(zone_45_only no)
(trace_min 0.0889)
@ -79,7 +79,7 @@
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFD7FFF)
(visible_elements FFFFFFFF)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
@ -860,7 +860,7 @@
(net 748 "Net-(J2-PadA2)")
(net_class Default "This is the default net class."
(clearance 0.0889)
(clearance 0.0762)
(trace_width 0.0889)
(via_dia 0.4)
(via_drill 0.2)
@ -1618,6 +1618,50 @@
(add_net ~PERST)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BF66684)
(at 88 53 270)
(descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x04 2.54mm single row")
(path /61FAF948/5C32CD1F)
(fp_text reference J10 (at 0 -2.33 270) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value UART (at 0 9.95 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 9.4) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end 1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
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(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
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(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 GND))
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 244 FTDI_D0_TX))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 62 FTDI_D1_RX))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 +3V3))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_USB:USB_C_Receptacle_Amphenol_12401610E4-2A (layer F.Cu) (tedit 5A142044) (tstamp 5CAA0D2E)
(at 44.6 51.8 270)
(descr "USB TYPE C, RA RCPT PCB, SMT, https://www.amphenolcanada.com/StockAvailabilityPrice.aspx?From=&PartNum=12401610E4%7e2A")
@ -13457,50 +13501,6 @@
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BF66684)
(at 88 53 270)
(descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x04 2.54mm single row")
(path /61FAF948/5C32CD1F)
(fp_text reference J10 (at 0 -2.33 270) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value UART (at 0 9.95 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 9.4) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end 1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
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(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 GND))
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 244 FTDI_D0_TX))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 62 FTDI_D1_RX))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 +3V3))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BF666CB)
(at 93 49 270)
(descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
@ -23703,6 +23703,60 @@
)
)
(gr_text V (at 94.25 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text O (at 91.75 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text C (at 89.25 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text I (at 86.75 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text M (at 84 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text G (at 81.5 47.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text V (at 89.5 51.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text R (at 86.5 51.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text T (at 84.25 51.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text G (at 81.75 51.75) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text V (at 81.75 58) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text S (at 84.25 58) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text C (at 86.75 58) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text G (at 89.5 58) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text 3 (at 89.5 55.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text 2 (at 86.75 55.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text 1 (at 84.25 55.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text 0 (at 81.75 55.5) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_line (start 126.7 81.5) (end 126.7 80.4) (layer B.SilkS) (width 0.15))
(gr_line (start 126.8 81.6) (end 126.7 81.5) (layer B.SilkS) (width 0.15))
(gr_line (start 126.8 81.8) (end 126.8 81.6) (layer B.SilkS) (width 0.15))
@ -23797,42 +23851,6 @@
(gr_text "PCIe 12V" (at 89.75 120.25) (layer F.SilkS) (tstamp 5C97E2E8)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text + (at 89.5 51.5) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text R (at 86.5 51.5) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text T (at 84 51.5) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text G (at 81.5 51.5) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text G (at 89.5 61) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text C (at 87 61) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text S (at 84.5 61) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text + (at 82 61) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text 3 (at 89.5 55) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text 2 (at 87 55) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text 1 (at 84.5 55) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text 0 (at 81.5 55) (layer In2.Cu)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_text CFG1 (at 89.5 91) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
@ -71488,7 +71506,7 @@
(segment (start 50.814264 50.53) (end 53.11 48.234264) (width 0.8) (layer In4.Cu) (net 736))
(segment (start 50.39 50.53) (end 50.814264 50.53) (width 0.8) (layer In4.Cu) (net 736))
(zone (net 21) (net_name GND) (layer In1.Cu) (tstamp 5C97CC50) (hatch edge 0.508)
(zone (net 21) (net_name GND) (layer In1.Cu) (tstamp 5CAC6F77) (hatch edge 0.508)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -79871,7 +79889,7 @@
)
)
)
(zone (net 21) (net_name GND) (layer In6.Cu) (tstamp 5C97CC4D) (hatch edge 0.508)
(zone (net 21) (net_name GND) (layer In6.Cu) (tstamp 5CAC6F74) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -86769,7 +86787,7 @@
)
)
)
(zone (net 21) (net_name GND) (layer B.Cu) (tstamp 5C97CC4A) (hatch edge 0.508)
(zone (net 21) (net_name GND) (layer B.Cu) (tstamp 5CAC6F71) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -92082,8 +92100,8 @@
)
(filled_polygon
(pts
(xy 180.919 112.192777) (xy 180.919 112.304) (xy 175.581 112.304) (xy 175.581 112.192777) (xy 175.561749 112.096)
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@ -92094,14 +92112,14 @@
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(filled_polygon
@ -93813,7 +93831,7 @@
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(zone (net 191) (net_name +1V2) (layer In4.Cu) (tstamp 5C97CC47) (hatch edge 0.508)
(zone (net 191) (net_name +1V2) (layer In4.Cu) (tstamp 5CAC6F6E) (hatch edge 0.508)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -97071,7 +97089,7 @@
)
)
)
(zone (net 190) (net_name +1V35) (layer In3.Cu) (tstamp 5C97CC44) (hatch edge 0.508)
(zone (net 190) (net_name +1V35) (layer In3.Cu) (tstamp 5CAC6F6B) (hatch edge 0.508)
(priority 2)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
@ -99708,7 +99726,7 @@
)
)
)
(zone (net 9) (net_name +3V3) (layer In3.Cu) (tstamp 5C97CC41) (hatch edge 0.508)
(zone (net 9) (net_name +3V3) (layer In3.Cu) (tstamp 5CAC6F68) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -111270,7 +111288,7 @@
)
)
)
(zone (net 223) (net_name DDR3_Vref) (layer In4.Cu) (tstamp 5C97CC3E) (hatch edge 0.508)
(zone (net 223) (net_name DDR3_Vref) (layer In4.Cu) (tstamp 5CAC6F65) (hatch edge 0.508)
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(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -112636,7 +112654,7 @@
)
)
)
(zone (net 7) (net_name /DDR3/DDR3_VTT) (layer In4.Cu) (tstamp 5C97CC3B) (hatch edge 0.508)
(zone (net 7) (net_name /DDR3/DDR3_VTT) (layer In4.Cu) (tstamp 5CAC6F62) (hatch edge 0.508)
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(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -113149,7 +113167,7 @@
)
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)
(zone (net 191) (net_name +1V2) (layer In4.Cu) (tstamp 5C97CC38) (hatch edge 0.508)
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@ -113707,7 +113725,7 @@
)
)
)
(zone (net 259) (net_name "/HDMI, GbE, USB/DVI_DVDD") (layer In4.Cu) (tstamp 5C97CC35) (hatch edge 0.508)
(zone (net 259) (net_name "/HDMI, GbE, USB/DVI_DVDD") (layer In4.Cu) (tstamp 5CAC6F5C) (hatch edge 0.508)
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(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -114019,7 +114037,7 @@
)
)
)
(zone (net 267) (net_name "/HDMI, GbE, USB/DVI_TVDD") (layer In4.Cu) (tstamp 5C97CC32) (hatch edge 0.508)
(zone (net 267) (net_name "/HDMI, GbE, USB/DVI_TVDD") (layer In4.Cu) (tstamp 5CAC6F59) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -114326,7 +114344,7 @@
)
)
)
(zone (net 102) (net_name "/FPGA IO/VCCIO7") (layer In4.Cu) (tstamp 5C97CC2F) (hatch edge 0.508)
(zone (net 102) (net_name "/FPGA IO/VCCIO7") (layer In4.Cu) (tstamp 5CAC6F56) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -114837,7 +114855,7 @@
)
)
)
(zone (net 115) (net_name "/FPGA IO/VCCIO6") (layer In4.Cu) (tstamp 5C97CC2C) (hatch edge 0.508)
(zone (net 115) (net_name "/FPGA IO/VCCIO6") (layer In4.Cu) (tstamp 5CAC6F53) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -115464,7 +115482,7 @@
)
)
)
(zone (net 413) (net_name "/FPGA Core Power/VCCA1") (layer In4.Cu) (tstamp 5C97CC29) (hatch edge 0.508)
(zone (net 413) (net_name "/FPGA Core Power/VCCA1") (layer In4.Cu) (tstamp 5CAC6F50) (hatch edge 0.508)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -115594,7 +115612,7 @@
)
)
)
(zone (net 412) (net_name "/FPGA Core Power/VCCAUX") (layer In3.Cu) (tstamp 5C97CC26) (hatch edge 0.508)
(zone (net 412) (net_name "/FPGA Core Power/VCCAUX") (layer In3.Cu) (tstamp 5CAC6F4D) (hatch edge 0.508)
(priority 16)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
@ -116138,7 +116156,7 @@
)
)
)
(zone (net 411) (net_name "/FPGA Core Power/VCCA0") (layer In4.Cu) (tstamp 5C97CC23) (hatch edge 0.508)
(zone (net 411) (net_name "/FPGA Core Power/VCCA0") (layer In4.Cu) (tstamp 5CAC6F4A) (hatch edge 0.508)
(connect_pads (clearance 0.15))
(min_thickness 0.15)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))

85
hardware/ecp5_mainboard/ecp5_mainboard.pro
Unescape View File

@ -1,29 +1,10 @@
update=22/05/2015 07:44:53
update=Tue 09 Apr 2019 10:52:46 BST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -31,3 +12,67 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=8
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.08889999999999999
MinViaDiameter=0.4
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.0889
TrackWidth2=0.1
TrackWidth3=0.15
TrackWidth4=0.2
TrackWidth5=0.25
TrackWidth6=0.35
TrackWidth7=0.5
TrackWidth8=0.8
TrackWidth9=1
ViaDiameter1=0.4
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.5
ViaDiameter4=1
ViaDrill4=0.6
ViaDiameter5=1.5
ViaDrill5=1
ViaDiameter6=2
ViaDrill6=1.5
dPairWidth1=0.11
dPairGap1=0.11
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0

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