Ivan Olenichev
3 years ago
parent
0c1894c8bd
commit
fbd2c1eab7
@ -0,0 +1,15 @@
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Copyright (C) 2018-2019 David Shah
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Modified ISC License to reflect hardware
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Permission to use, copy, modify, and/or distribute this hardware design and
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software for any purpose with or without fee is hereby granted, provided that
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the above copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
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FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
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OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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PERFORMANCE OF THIS SOFTWARE.
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@ -0,0 +1,21 @@
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${KICAD6_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Coilcraft_XAL60xx_6.36x6.56mm.wrl
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${KICAD6_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Coilcraft_XAL5030.wrl
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${KICAD6_3DMODEL_DIR}/Connector_RJ.3dshapes/RJ45_Pulse_JK0654219NL_Horizontal.wrl
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${KICAD6_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Vishay_IHLP-1212.wrl
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${KICAD6_3DMODEL_DIR}/Connector_BarrelJack.3dshapes/BarrelJack_Horizontal.wrl
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${KICAD6_3DMODEL_DIR}/Oscillator.3dshapes/Oscillator_SMD_IDT_JS6-6_5.0x3.2mm_P1.27mm.wrl
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${KICAD6_3DMODEL_DIR}/LED_SMD.3dshapes/LED_RGB_Wuerth-PLCC4_3.2x2.8mm_150141M173100.wrl
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${KICAD6_3DMODEL_DIR}/Connector_FFC-FPC.3dshapes/TE_4-1734839-0_1x40-1MP_P0.5mm_Horizontal.wrl
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${KICAD6_3DMODEL_DIR}/Connector_USB.3dshapes/USB_C_Receptacle_Amphenol_12401610E4-2A.wrl
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${KICAD6_3DMODEL_DIR}/Package_BGA.3dshapes/Lattice_caBGA-756_27.0x27.0mm_Layout32x32_P0.8mm.wrl
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${KICAD6_3DMODEL_DIR}/Connector_Card.3dshapes/microSD_HC_Hirose_DM3AT-SF-PEJM5.wrl
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Custom Parts:292303-7
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Custom Parts:Molex_HDMI_A_47151-0001
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Custom Parts:FuseHolder_SMD_Shurter_0031.7701.11
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Custom Parts:2199230-4
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https://gitlab.com/kicad/libraries/kicad-footprints/-/merge_requests/1404
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https://gitlab.com/kicad/libraries/kicad-footprints/-/merge_requests/1929 (mine, closed, duplicate)
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Custom Parts:9774025151R
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@ -0,0 +1,36 @@
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# Ultimate ECP5 Board
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WIP - Rev 1.0 prototypes currently under test...
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## Key Features
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- Largest ECP5; LFE5UM5G-85F
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- PCIe 2.0 x2 card edge connector on two SERDES channels
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- Remaining two SERDES channels on M.2 E-key connector
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- 1GByte x32 DDR3L (two x16 chips)
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- Dedicated HDMI output, using TFP410 serialiser
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- 1000BASE-T GbE connector with RGMII PHY
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- USB-A 2.0 host connector with ULPI PHY
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- FT2232H for debug JTAG and UART/FIFO with type-C connector
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- PCIe, external 12V or USB power input
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- 12 bicolour (tristate) user LEDs, 4 user buttons, 8 user DIP switches
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- 128Mbit QSPI flash for boot and data
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- microSD card connector
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- Dual PMOD connector with extra "middle" IO pins
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- As many remaining IO as possible on high speed FFC connectors with a differential optimised pinout (3x 24 IO). Selectable 1.8V/2.5V/3.3V
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## Layout
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- PCIe card form factor
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- At least Ethernet, USB-A, USB type-C power/debug and HDMI out
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- Other connectors probably would have to be on other sides. FFC connectors probably on top so they can loop over to another card to form a 2-slot card (e.g. with ADCs/DACs for SDR/DAQ)
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## Possible accessories using high-speed FFC connectors
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- MIPI DSI smartphone-style LCDs
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- MIPI CSI-2 cameras
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- High speed ADC/DAC
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- HDMI in/out, direct or using serialiser chip
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- LVDS video in/out for LCDs or block cameras
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- Breakout board to dual or triple PMOD
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@ -0,0 +1,271 @@
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# This file is Copyright (c) 2019 David Shah <dave@ds0.me>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("B29"), IOStandard("LVDS")),
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("clk12", 0, Pins("B3"), IOStandard("LVCMOS33")),
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("clkref", 0, Pins("E17"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("Y32"), IOStandard("SSTL135_I")),
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("user_btn", 1, Pins("W31"), IOStandard("SSTL135_I")),
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("user_btn", 2, Pins("AD30"), IOStandard("SSTL135_I")),
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("user_btn", 3, Pins("AD29"), IOStandard("SSTL135_I")),
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("user_dip", 0, Pins("AE31"), IOStandard("SSTL135_I")),
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("user_dip", 1, Pins("AE32"), IOStandard("SSTL135_I")),
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("user_dip", 2, Pins("AD32"), IOStandard("SSTL135_I")),
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("user_dip", 3, Pins("AC32"), IOStandard("SSTL135_I")),
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("user_dip", 4, Pins("AB32"), IOStandard("SSTL135_I")),
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("user_dip", 5, Pins("AB31"), IOStandard("SSTL135_I")),
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("user_dip", 6, Pins("AC31"), IOStandard("SSTL135_I")),
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("user_dip", 7, Pins("AC30"), IOStandard("SSTL135_I")),
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("user_led", 0, Pins("C26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D26"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A28"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("A29"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("A30"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("AK29"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("AH32"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("AH30"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("AH28"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("AG30"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("AG29"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("AK30"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("rx", Pins("AM28"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("AL28"), IOStandard("LVCMOS33")),
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),
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("ftdi", 0,
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Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")),
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Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")),
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Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")),
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Subsignal("rd_n", Pins("AL32"), IOStandard("LVCMOS33")),
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Subsignal("wr_n", Pins("AG28"), IOStandard("LVCMOS33")),
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Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"E30 F28 C32 E29 F32 D30 E32 D29",
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"D32 C31 H32 F31 F29 B32 D31"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("H31 H30 J30"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("K31"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("K30"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("J32"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("K29"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("R26 L27 Y27 U31"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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" V26 R27 V27 T26 U28 T27 T29 U26",
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" P27 K28 P26 L26 K27 N26 L29 K26",
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"AC27 W28 AC26 Y26 AB26 W29 AD26 Y28",
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" T32 U32 P31 V32 P32 W32 N32 U30"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("R29 N30 AB28 R32"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("L31"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("K32"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("J29"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("L32"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST"),
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),
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("dram_vtt_en", 0, Pins("E25"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("A15")),
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Subsignal("rx", Pins("C17")),
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Subsignal("ref", Pins("A17")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("D16")),
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Subsignal("int_n", Pins("E16")),
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Subsignal("mdio", Pins("F17")),
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Subsignal("mdc", Pins("B17")),
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Subsignal("rx_ctl", Pins("A16")),
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Subsignal("rx_data", Pins("C16 B16 B14 F16")),
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Subsignal("tx_ctl", Pins("D15")),
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Subsignal("tx_data", Pins("A14 F15 C15 C14")),
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IOStandard("LVCMOS33")
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),
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("clkgen", 0,
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Subsignal("sda", Pins("C22")),
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Subsignal("scl", Pins("A22")),
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Subsignal("sd_oe", Pins("A2")),
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IOStandard("LVCMOS33")
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),
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("pcie_x2", 0,
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Subsignal("clk_p", Pins("AM14")),
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Subsignal("clk_n", Pins("AM15")),
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Subsignal("rx_p", Pins("AM8 AK12")),
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Subsignal("rx_n", Pins("AM9 AK13")),
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Subsignal("tx_p", Pins("AK9 AM11")),
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Subsignal("tx_n", Pins("AK10 AM12")),
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Subsignal("perst", Pins("D22"), IOStandard("LVCMOS33")),
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Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")),
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),
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("m2", 0,
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Subsignal("clk_p", Pins("AM23")),
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Subsignal("clk_n", Pins("AM24")),
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Subsignal("rx_p", Pins("AM17 AK21")),
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Subsignal("rx_n", Pins("AM18 AK22")),
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Subsignal("tx_p", Pins("AK18 AM20")),
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Subsignal("tx_n", Pins("AK19 AM21")),
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Subsignal("clksel", Pins("N3"), IOStandard("LVCMOS33")),
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Subsignal("sdio_clk", Pins("L4"), IOStandard("LVCMOS33")),
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Subsignal("sdio_cmd", Pins("K4"), IOStandard("LVCMOS33")),
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Subsignal("sdio_dq", Pins("L7 N4 L6 N6"), IOStandard("LVCMOS33")),
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Subsignal("uart_tx", Pins("P6"), IOStandard("LVCMOS33")),
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Subsignal("uart_rx", Pins("K5"), IOStandard("LVCMOS33")),
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Subsignal("uart_rts_n", Pins("N7"), IOStandard("LVCMOS33")),
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Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33"))
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),
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("sdcard", 0,
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Subsignal("data", Pins("AG1 AJ1 AH1 AK1")),
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Subsignal("clk", Pins("AK3")),
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Subsignal("cmd", Pins("AH3")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("clk", Pins("AM3")),
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Subsignal("cs_n", Pins("AJ3")),
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Subsignal("dq", Pins("AK2 AJ2 AM2 AL1")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("clk", Pins("AM3")),
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Subsignal("cs_n", Pins("AJ3")),
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Subsignal("mosi", Pins("AK2")),
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Subsignal("miso", Pins("AJ2")),
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Subsignal("wp", Pins("AM2")),
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Subsignal("hold", Pins("AL1")),
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IOStandard("LVCMOS33")
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),
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("ulpi", 0,
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Subsignal("clk", Pins("A18")),
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Subsignal("stp", Pins("D18")),
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Subsignal("dir", Pins("C18")),
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Subsignal("nxt", Pins("F18")),
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Subsignal("reset", Pins("D17")),
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Subsignal("data", Pins("C20 C19 E19 D20 A20 B19 D19 A19")),
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IOStandard("LVCMOS33")
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),
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("hdmi", 0,
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Subsignal("d", Pins(
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"C11 A11 B11 A10 B10 C10 A8 B7",
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"B8 A7 C8 C9 F11 E11 E10 D10",
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"F10 F9 D9 D8 C7 F8 E8 D11")),
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Subsignal("de", Pins("F14")),
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Subsignal("clk", Pins("A9")),
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Subsignal("vsync", Pins("E14")),
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Subsignal("hsync", Pins("F13")),
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Subsignal("sda", Pins("D13")),
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Subsignal("scl", Pins("C13")),
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IOStandard("LVCMOS33")
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),
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]
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_connectors = [
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("pmoda", "F19 F20 B22 C23 D14 A13 E22 D23"),
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("pmodb", "C25 A26 F23 F25 B25 D25 F22 F24"),
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("pmodx", "A24 C24 D24 B23 D23 A25"),
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("ext0", "T1 U1 AE5 AE4 AB5 AB6 Y5 W5 W2 Y1 AB7 AC6 AB3 AB4 AD3 AE3 AB1 AC1 AD1 AE1 AD6 AE6 AC7 AD7"),
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("ext1", "P5 P4 R7 T7 R6 T6 U6 U7 R4 T5 T4 U5 U4 V4 V6 V7 P2 P3 R3 T3 N1 P1 U2 U3"),
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("ext2", "K6 K7 J7 J6 H6 H5 F4 F5 F3 E3 C4 C3 C5 D5 D3 D2 H2 H3 J3 K3 B1 C2 F1 H1")
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs)
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
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except ConstraintError:
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pass
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def create_programmer(self, with_ispclock=True):
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_xcf_ispclock = """
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<Device>
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<SelectedProg value="FALSE"/>
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<Pos>2</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ispCLOCK</Family>
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<Name>ispPAC-CLK5406D</Name>
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<IDCode>0x00191043</IDCode>
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<Operation>Erase,Program,Verify</Operation>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Device>
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"""
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.4.1">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>ECP5UM5G</Family>
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<Name>LFE5UM5G-45F</Name>
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<IDCode>0x81112043</IDCode>
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<File>{{bitstream_file}}</File>
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<Operation>Fast Program</Operation>
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</Device>{ispclock}
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
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</CableOptions>
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</ispXCF>
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""".format(ispclock=_xcf_ispclock if with_ispclock else "")
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return LatticeProgrammer(_xcf_template)
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@ -0,0 +1,16 @@
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# TrellisBoard OpenOCD config
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interface ftdi
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# ftdi_device_desc "TrellisBoard"
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ftdi_vid_pid 0x0403 0x6010
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# channel 1 does not have any functionality
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ftdi_channel 0
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# just TCK TDI TDO TMS, no reset
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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# default speed
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adapter_khz 5000
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# ECP5 device - LFE5UM5G-85F
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
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@ -0,0 +1,4 @@
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*.json
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*_out.config
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*.bit
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*.svf
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@ -0,0 +1,22 @@
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PROJ=demo
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all: ${PROJ}.bit
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%.json: *.v
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yosys -p "synth_ecp5 -json $@ -top $*_top" $^
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%_out.config: %.json
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nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --package CABGA756 --lpf trellisboard.lpf
|
||||
|
||||
%.bit: %_out.config
|
||||
ecppack --svf ${PROJ}.svf $< $@
|
||||
|
||||
${PROJ}.svf : ${PROJ}.bit
|
||||
|
||||
prog: ${PROJ}.svf
|
||||
openocd -f ../misc/trellisboard.cfg -c "transport select jtag; init; svf $<; exit"
|
||||
|
||||
clean:
|
||||
rm -f *.svf *.bit *.config *.json
|
||||
|
||||
.PHONY: prog clean
|
||||
@ -0,0 +1,47 @@
|
||||
`default_nettype none
|
||||
|
||||
module demo_top(
|
||||
input clk_12,
|
||||
input [3:0] btn,
|
||||
input [7:0] dip_sw,
|
||||
output [11:0] led
|
||||
);
|
||||
|
||||
reg [35:0] ctr_scroll;
|
||||
reg [35:0] ctr_scroll_swapped;
|
||||
reg clk_div = 0;
|
||||
|
||||
localparam DIV = 20;
|
||||
reg [DIV-1:0] div_ctr = 0;
|
||||
|
||||
always @(posedge clk_12) begin
|
||||
{clk_div, div_ctr} <= div_ctr + 1'b1;
|
||||
|
||||
if (clk_div) begin
|
||||
if (!(|ctr_scroll))
|
||||
ctr_scroll <= {1'b1, {10{1'b0}}, 1'b1, {13{1'b0}}, 1'b1};
|
||||
else
|
||||
ctr_scroll <= {ctr_scroll[34:24], ctr_scroll[35],
|
||||
ctr_scroll[22:12], ctr_scroll[23],
|
||||
ctr_scroll[10:0], ctr_scroll[11]};
|
||||
end
|
||||
end
|
||||
|
||||
integer i, j;
|
||||
always @(posedge clk_12) begin
|
||||
for (i = 0; i < 36; i = i + 6)
|
||||
for (j = 0; j < 6; j = j + 1)
|
||||
if ((i % 12) == 0)
|
||||
ctr_scroll_swapped[i+j] <= ctr_scroll[i+j];
|
||||
else
|
||||
ctr_scroll_swapped[i+j] <= ctr_scroll[i+5-j];
|
||||
end
|
||||
|
||||
led_ctrl led_ctrl_i (
|
||||
.clk(clk_12),
|
||||
.led_in_yr({ctr_scroll_swapped[23:12] | ctr_scroll_swapped[35:24]}),
|
||||
.led_in_bg({ctr_scroll_swapped[11:0] | ctr_scroll_swapped[35:24]}),
|
||||
.led_pin(led)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,43 @@
|
||||
// LED multiplex control
|
||||
|
||||
module led_ctrl (
|
||||
// Fast clock (12MHz+)
|
||||
input clk,
|
||||
// Colour A inputs (yellow for 0-5, red for 6-11)
|
||||
input [11:0] led_in_yr,
|
||||
// Colour B inputs (blue for 0-5, green for 6-11)
|
||||
input [11:0] led_in_bg,
|
||||
// Output to LED pins
|
||||
output [11:0] led_pin
|
||||
);
|
||||
// Gives ~23kHz at 12MHz, ~195kHz at 100MHz
|
||||
localparam DIV_FACTOR = 9;
|
||||
reg [DIV_FACTOR-1:0] ctr;
|
||||
|
||||
always @(posedge clk) ctr <= ctr + 1'b1;
|
||||
|
||||
wire pwm_1_4 = ctr[DIV_FACTOR - 1 : DIV_FACTOR - 2] > 2'b10;
|
||||
wire pwm_7_8 = ctr[DIV_FACTOR - 1 : DIV_FACTOR - 3] > 2'b000;
|
||||
|
||||
|
||||
genvar i;
|
||||
wire [11:0] led_o, led_en;
|
||||
generate
|
||||
for (i = 0; i < 12; i = i + 1'b1) begin
|
||||
/*
|
||||
Only YR asserted : LED at constant 1'b0
|
||||
Both YR & BG asserted : blend colour by connecting LED to divider MSB
|
||||
NB: bias towards yellow (i<6) or green (i>=6) for better white/orange
|
||||
Only BG asserted : LED at constant 1'b1
|
||||
Neither asserted : LED off (1'bz)
|
||||
*/
|
||||
assign led_o[i] = led_in_yr[i] ?
|
||||
(led_in_bg[i] ? (i < 6 ? pwm_1_4 : pwm_7_8) : 1'b0) :
|
||||
1'b1;
|
||||
assign led_en[i] = led_in_yr[i] || led_in_bg[i];
|
||||
assign led_pin[i] = led_en[i] ? led_o[i] : 1'bz;
|
||||
//BB bb_i (.I(led_o[i]), .T(~led_en[i]), .B(led_pin[i]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@ -0,0 +1,56 @@
|
||||
LOCATE COMP "clk_12" SITE "B3";
|
||||
IOBUF PORT "clk_12" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "btn[0]" SITE "Y32";
|
||||
LOCATE COMP "btn[1]" SITE "W31";
|
||||
LOCATE COMP "btn[2]" SITE "AD30";
|
||||
LOCATE COMP "btn[3]" SITE "AD29";
|
||||
|
||||
IOBUF PORT "btn[0]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "btn[1]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "btn[2]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "btn[3]" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "dip_sw[0]" SITE "AE31";
|
||||
LOCATE COMP "dip_sw[1]" SITE "AE32";
|
||||
LOCATE COMP "dip_sw[2]" SITE "AD32";
|
||||
LOCATE COMP "dip_sw[3]" SITE "AC32";
|
||||
LOCATE COMP "dip_sw[4]" SITE "AB32";
|
||||
LOCATE COMP "dip_sw[5]" SITE "AB31";
|
||||
LOCATE COMP "dip_sw[6]" SITE "AC31";
|
||||
LOCATE COMP "dip_sw[7]" SITE "AC30";
|
||||
|
||||
IOBUF PORT "dip_sw[0]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[1]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[2]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[3]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[4]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[5]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[6]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "dip_sw[7]" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "led[0]" SITE "C26";
|
||||
LOCATE COMP "led[1]" SITE "D26";
|
||||
LOCATE COMP "led[2]" SITE "A28";
|
||||
LOCATE COMP "led[3]" SITE "A29";
|
||||
LOCATE COMP "led[4]" SITE "A30";
|
||||
LOCATE COMP "led[5]" SITE "AK29";
|
||||
LOCATE COMP "led[6]" SITE "AH32";
|
||||
LOCATE COMP "led[7]" SITE "AH30";
|
||||
LOCATE COMP "led[8]" SITE "AH28";
|
||||
LOCATE COMP "led[9]" SITE "AG30";
|
||||
LOCATE COMP "led[10]" SITE "AG29";
|
||||
LOCATE COMP "led[11]" SITE "AK30";
|
||||
|
||||
IOBUF PORT "led[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
IOBUF PORT "led[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE;
|
||||
Loading…
Reference in new issue