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fs-ulx3s/ulx3s.kicad_pcb-bak

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screw holes proper spacing for M3
8 years ago
(kicad_pcb (version 4) (host pcbnew 4.0.5+dfsg1-4)
(general
shrinking the board
8 years ago
(links 238)
(no_connects 237)
reverting layout back to original, just a bit larger board that fits M3 screws
8 years ago
(area 86.329999 53.649999 185.690001 109.830001)
screw holes proper spacing for M3
8 years ago
(thickness 1.6)
(drawings 20)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(tracks 6)
screw holes proper spacing for M3
8 years ago
(zones 0)
(modules 13)
chip name edited on JTAG to be the same as all units
8 years ago
(nets 76)
screw holes proper spacing for M3
8 years ago
)
(page A4)
(layers
(0 F.Cu signal)
(1 In1.Cu signal)
(2 In2.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
changing BANK0 (Unit A) shematic symbol and adding BANK1 (Unit B)
8 years ago
(edge_width 0.2)
screw holes proper spacing for M3
8 years ago
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed yes)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 82.67 62.69)
(grid_origin 86.48 79.2)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(visible_elements 7FFFFFFF)
screw holes proper spacing for M3
8 years ago
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 GND)
(net 2 VCC)
(net 3 /TDI)
(net 4 /TCK)
(net 5 /TMS)
(net 6 /TDO)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 7 +5V)
(net 8 /USB5V)
(net 9 "Net-(D4-Pad1)")
(net 10 /gpio/IN5V)
(net 11 /gpio/OUT5V)
(net 12 /gpio/P5)
(net 13 /gpio/P6)
(net 14 /gpio/P7)
(net 15 /gpio/P8)
(net 16 /gpio/P11)
(net 17 /gpio/P12)
(net 18 /gpio/P13)
(net 19 /gpio/P14)
(net 20 /gpio/P17)
(net 21 /gpio/P18)
(net 22 /gpio/P19)
(net 23 /gpio/P20)
(net 24 /gpio/P21)
(net 25 /gpio/P22)
(net 26 /gpio/P23)
(net 27 /gpio/P24)
(net 28 /gpio/P25)
(net 29 /gpio/P26)
(net 30 /gpio/P27)
(net 31 /gpio/P28)
(net 32 /gpio/P29)
(net 33 /gpio/P30)
(net 34 /SD_3)
(net 35 /MTMS)
(net 36 /MTCK)
(net 37 /MTDO)
(net 38 /MTDI)
(net 39 /gpio/P9)
(net 40 /gpio/P10)
(net 41 "Net-(GPDI1-PadSHD)")
(net 42 "Net-(US1-Pad6)")
(net 43 "Net-(US2-Pad6)")
chip name edited on JTAG to be the same as all units
8 years ago
(net 44 /gpio/P15)
(net 45 /gpio/P16)
(net 46 /gpio/P31)
(net 47 /gpio/P32)
(net 48 /gpio/P33)
(net 49 /gpio/P34)
(net 50 /gpio/P35)
(net 51 /gpio/P36)
(net 52 /gpio/P37)
(net 53 /gpio/P38)
(net 54 /gpio/P39)
(net 55 /gpio/P40)
(net 56 /gpio/P41)
(net 57 /gpio/P42)
(net 58 /gpio/P43)
(net 59 /gpio/P44)
(net 60 /gpio/P45)
(net 61 /gpio/P46)
(net 62 /gpio/P47)
(net 63 /gpio/P48)
(net 64 /gpio/P49)
(net 65 /gpio/P50)
(net 66 /gpio/P51)
(net 67 /gpio/P52)
(net 68 /gpio/P53)
(net 69 /gpio/P54)
(net 70 /gpio/P55)
(net 71 /gpio/P56)
(net 72 /gpio/P57)
(net 73 /gpio/P58)
(net 74 /gpio/P59)
(net 75 /gpio/P60)
screw holes proper spacing for M3
8 years ago
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +5V)
(add_net /MTCK)
(add_net /MTDI)
(add_net /MTDO)
(add_net /MTMS)
(add_net /SD_3)
(add_net /TCK)
(add_net /TDI)
(add_net /TDO)
(add_net /TMS)
(add_net /USB5V)
(add_net /gpio/IN5V)
(add_net /gpio/OUT5V)
(add_net /gpio/P10)
(add_net /gpio/P11)
(add_net /gpio/P12)
(add_net /gpio/P13)
(add_net /gpio/P14)
chip name edited on JTAG to be the same as all units
8 years ago
(add_net /gpio/P15)
(add_net /gpio/P16)
screw holes proper spacing for M3
8 years ago
(add_net /gpio/P17)
(add_net /gpio/P18)
(add_net /gpio/P19)
(add_net /gpio/P20)
(add_net /gpio/P21)
(add_net /gpio/P22)
(add_net /gpio/P23)
(add_net /gpio/P24)
(add_net /gpio/P25)
(add_net /gpio/P26)
(add_net /gpio/P27)
(add_net /gpio/P28)
(add_net /gpio/P29)
(add_net /gpio/P30)
chip name edited on JTAG to be the same as all units
8 years ago
(add_net /gpio/P31)
(add_net /gpio/P32)
(add_net /gpio/P33)
(add_net /gpio/P34)
(add_net /gpio/P35)
(add_net /gpio/P36)
(add_net /gpio/P37)
(add_net /gpio/P38)
(add_net /gpio/P39)
(add_net /gpio/P40)
(add_net /gpio/P41)
(add_net /gpio/P42)
(add_net /gpio/P43)
(add_net /gpio/P44)
(add_net /gpio/P45)
(add_net /gpio/P46)
(add_net /gpio/P47)
(add_net /gpio/P48)
(add_net /gpio/P49)
screw holes proper spacing for M3
8 years ago
(add_net /gpio/P5)
chip name edited on JTAG to be the same as all units
8 years ago
(add_net /gpio/P50)
(add_net /gpio/P51)
(add_net /gpio/P52)
(add_net /gpio/P53)
(add_net /gpio/P54)
(add_net /gpio/P55)
(add_net /gpio/P56)
(add_net /gpio/P57)
(add_net /gpio/P58)
(add_net /gpio/P59)
screw holes proper spacing for M3
8 years ago
(add_net /gpio/P6)
chip name edited on JTAG to be the same as all units
8 years ago
(add_net /gpio/P60)
screw holes proper spacing for M3
8 years ago
(add_net /gpio/P7)
(add_net /gpio/P8)
(add_net /gpio/P9)
(add_net "Net-(D4-Pad1)")
(add_net "Net-(GPDI1-PadSHD)")
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(add_net "Net-(US1-Pad6)")
(add_net "Net-(US2-Pad6)")
screw holes proper spacing for M3
8 years ago
(add_net VCC)
)
(net_class BGA ""
(clearance 0.1)
(trace_width 0.2)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GND)
)
(module SMD_Packages:SMD-1206_Pol (layer B.Cu) (tedit 0) (tstamp 56AA106E)
(at 119.093 91.676)
(path /56AC389C/56AC4846)
(attr smd)
(fp_text reference D2 (at 0 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 2A (at 0 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.54 1.143) (end -2.794 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 1.143) (end -2.794 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 -1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 -1.143) (end -0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 0.889 1.143) (end 2.54 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 1.143) (end 2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 -1.143) (end 0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -0.889 1.143) (end -2.54 1.143) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.651 0) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 11 /gpio/OUT5V))
(pad 2 smd rect (at 1.651 0) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask))
screw holes proper spacing for M3
8 years ago
(model SMD_Packages.3dshapes/SMD-1206_Pol.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:SMD-1206_Pol (layer B.Cu) (tedit 0) (tstamp 56AA1068)
(at 119.093 82.476)
(path /56AC389C/56AC483B)
(attr smd)
(fp_text reference D1 (at 0 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 2A (at 0 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.54 1.143) (end -2.794 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 1.143) (end -2.794 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 -1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 -1.143) (end -0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 0.889 1.143) (end 2.54 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 1.143) (end 2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 -1.143) (end 0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -0.889 1.143) (end -2.54 1.143) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.651 0) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 7 +5V))
screw holes proper spacing for M3
8 years ago
(pad 2 smd rect (at 1.651 0) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 10 /gpio/IN5V))
screw holes proper spacing for M3
8 years ago
(model SMD_Packages.3dshapes/SMD-1206_Pol.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module lfe5bg381:BGA-381_pitch0.8mm_dia0.4mm (layer F.Cu) (tedit 56A8C998) (tstamp 56AA0CD9)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(at 135.48 84.8)
screw holes proper spacing for M3
8 years ago
(path /56AA9804)
(attr smd)
(fp_text reference U1 (at -7.6 -9.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
shrinking the board
8 years ago
(fp_text value LFE5U-25F-6BG381C (at 2 -9.2) (layer F.Fab)
screw holes proper spacing for M3
8 years ago
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -8.4 8.4) (end 8.4 8.4) (layer F.SilkS) (width 0.15))
(fp_line (start 8.4 8.4) (end 8.4 -8.4) (layer F.SilkS) (width 0.15))
(fp_line (start 8.4 -8.4) (end -8.4 -8.4) (layer F.SilkS) (width 0.15))
(fp_line (start -8.4 -8.4) (end -8.4 8.4) (layer F.SilkS) (width 0.15))
(fp_line (start -7.6 -8.4) (end -8.4 -7.6) (layer F.SilkS) (width 0.15))
(pad A2 smd circle (at -6.8 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad A3 smd circle (at -6 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad A4 smd circle (at -5.2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad A5 smd circle (at -4.4 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad A6 smd circle (at -3.6 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 31 /gpio/P28))
screw holes proper spacing for M3
8 years ago
(pad A7 smd circle (at -2.8 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 45 /gpio/P16))
screw holes proper spacing for M3
8 years ago
(pad A8 smd circle (at -2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 44 /gpio/P15))
screw holes proper spacing for M3
8 years ago
(pad A9 smd circle (at -1.2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 40 /gpio/P10))
screw holes proper spacing for M3
8 years ago
(pad A10 smd circle (at -0.4 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 14 /gpio/P7))
screw holes proper spacing for M3
8 years ago
(pad A11 smd circle (at 0.4 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 15 /gpio/P8))
chip name edited on JTAG to be the same as all units
8 years ago
(pad A12 smd circle (at 1.2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 69 /gpio/P54))
(pad A13 smd circle (at 2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 68 /gpio/P53))
(pad A14 smd circle (at 2.8 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 63 /gpio/P48))
screw holes proper spacing for M3
8 years ago
(pad A15 smd circle (at 3.6 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
chip name edited on JTAG to be the same as all units
8 years ago
(pad A16 smd circle (at 4.4 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 55 /gpio/P40))
(pad A17 smd circle (at 5.2 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 49 /gpio/P34))
(pad A18 smd circle (at 6 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 47 /gpio/P32))
(pad A19 smd circle (at 6.8 -7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 33 /gpio/P30))
screw holes proper spacing for M3
8 years ago
(pad B1 smd circle (at -7.6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad B2 smd circle (at -6.8 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad B3 smd circle (at -6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad B4 smd circle (at -5.2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad B5 smd circle (at -4.4 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad B6 smd circle (at -3.6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 30 /gpio/P27))
screw holes proper spacing for M3
8 years ago
(pad B7 smd circle (at -2.8 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad B8 smd circle (at -2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 20 /gpio/P17))
screw holes proper spacing for M3
8 years ago
(pad B9 smd circle (at -1.2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 17 /gpio/P12))
screw holes proper spacing for M3
8 years ago
(pad B10 smd circle (at -0.4 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 39 /gpio/P9))
screw holes proper spacing for M3
8 years ago
(pad B11 smd circle (at 0.4 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 12 /gpio/P5))
chip name edited on JTAG to be the same as all units
8 years ago
(pad B12 smd circle (at 1.2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 73 /gpio/P58))
(pad B13 smd circle (at 2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 67 /gpio/P52))
screw holes proper spacing for M3
8 years ago
(pad B14 smd circle (at 2.8 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
chip name edited on JTAG to be the same as all units
8 years ago
(pad B15 smd circle (at 3.6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 59 /gpio/P44))
(pad B16 smd circle (at 4.4 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 54 /gpio/P39))
(pad B17 smd circle (at 5.2 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 51 /gpio/P36))
(pad B18 smd circle (at 6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 48 /gpio/P33))
(pad B19 smd circle (at 6.8 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 46 /gpio/P31))
(pad B20 smd circle (at 7.6 -6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 32 /gpio/P29))
screw holes proper spacing for M3
8 years ago
(pad C1 smd circle (at -7.6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C2 smd circle (at -6.8 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C3 smd circle (at -6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C4 smd circle (at -5.2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C5 smd circle (at -4.4 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C6 smd circle (at -3.6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 25 /gpio/P22))
screw holes proper spacing for M3
8 years ago
(pad C7 smd circle (at -2.8 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 24 /gpio/P21))
screw holes proper spacing for M3
8 years ago
(pad C8 smd circle (at -2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 21 /gpio/P18))
screw holes proper spacing for M3
8 years ago
(pad C9 smd circle (at -1.2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C10 smd circle (at -0.4 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 16 /gpio/P11))
screw holes proper spacing for M3
8 years ago
(pad C11 smd circle (at 0.4 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 13 /gpio/P6))
chip name edited on JTAG to be the same as all units
8 years ago
(pad C12 smd circle (at 1.2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 72 /gpio/P57))
(pad C13 smd circle (at 2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 66 /gpio/P51))
(pad C14 smd circle (at 2.8 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 62 /gpio/P47))
(pad C15 smd circle (at 3.6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 58 /gpio/P43))
(pad C16 smd circle (at 4.4 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 53 /gpio/P38))
(pad C17 smd circle (at 5.2 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 50 /gpio/P35))
screw holes proper spacing for M3
8 years ago
(pad C18 smd circle (at 6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad C19 smd circle (at 6.8 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad C20 smd circle (at 7.6 -6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D1 smd circle (at -7.6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D2 smd circle (at -6.8 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D3 smd circle (at -6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D4 smd circle (at -5.2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad D5 smd circle (at -4.4 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D6 smd circle (at -3.6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 28 /gpio/P25))
chip name edited on JTAG to be the same as all units
8 years ago
(pad D7 smd circle (at -2.8 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 26 /gpio/P23))
screw holes proper spacing for M3
8 years ago
(pad D8 smd circle (at -2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 22 /gpio/P19))
screw holes proper spacing for M3
8 years ago
(pad D9 smd circle (at -1.2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 19 /gpio/P14))
screw holes proper spacing for M3
8 years ago
(pad D10 smd circle (at -0.4 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
chip name edited on JTAG to be the same as all units
8 years ago
(pad D11 smd circle (at 0.4 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 75 /gpio/P60))
(pad D12 smd circle (at 1.2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 71 /gpio/P56))
(pad D13 smd circle (at 2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 65 /gpio/P50))
(pad D14 smd circle (at 2.8 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 61 /gpio/P46))
(pad D15 smd circle (at 3.6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 57 /gpio/P42))
(pad D16 smd circle (at 4.4 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 52 /gpio/P37))
screw holes proper spacing for M3
8 years ago
(pad D17 smd circle (at 5.2 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D18 smd circle (at 6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D19 smd circle (at 6.8 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad D20 smd circle (at 7.6 -5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E1 smd circle (at -7.6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E2 smd circle (at -6.8 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E3 smd circle (at -6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E4 smd circle (at -5.2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E5 smd circle (at -4.4 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E6 smd circle (at -3.6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 29 /gpio/P26))
chip name edited on JTAG to be the same as all units
8 years ago
(pad E7 smd circle (at -2.8 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 27 /gpio/P24))
screw holes proper spacing for M3
8 years ago
(pad E8 smd circle (at -2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
chip name edited on JTAG to be the same as all units
8 years ago
(net 23 /gpio/P20))
screw holes proper spacing for M3
8 years ago
(pad E9 smd circle (at -1.2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 18 /gpio/P13))
screw holes proper spacing for M3
8 years ago
(pad E10 smd circle (at -0.4 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
chip name edited on JTAG to be the same as all units
8 years ago
(pad E11 smd circle (at 0.4 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 74 /gpio/P59))
(pad E12 smd circle (at 1.2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 70 /gpio/P55))
(pad E13 smd circle (at 2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 64 /gpio/P49))
(pad E14 smd circle (at 2.8 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 60 /gpio/P45))
(pad E15 smd circle (at 3.6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 56 /gpio/P41))
screw holes proper spacing for M3
8 years ago
(pad E16 smd circle (at 4.4 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E17 smd circle (at 5.2 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E18 smd circle (at 6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E19 smd circle (at 6.8 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad E20 smd circle (at 7.6 -4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F1 smd circle (at -7.6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F2 smd circle (at -6.8 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F3 smd circle (at -6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F4 smd circle (at -5.2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F5 smd circle (at -4.4 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F6 smd circle (at -3.6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F7 smd circle (at -2.8 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad F8 smd circle (at -2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad F9 smd circle (at -1.2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F10 smd circle (at -0.4 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F11 smd circle (at 0.4 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F12 smd circle (at 1.2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F13 smd circle (at 2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad F14 smd circle (at 2.8 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad F15 smd circle (at 3.6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad F16 smd circle (at 4.4 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F17 smd circle (at 5.2 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F18 smd circle (at 6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F19 smd circle (at 6.8 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad F20 smd circle (at 7.6 -3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G1 smd circle (at -7.6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G2 smd circle (at -6.8 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G3 smd circle (at -6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G4 smd circle (at -5.2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G5 smd circle (at -4.4 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G6 smd circle (at -3.6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G7 smd circle (at -2.8 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G8 smd circle (at -2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G9 smd circle (at -1.2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G10 smd circle (at -0.4 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G11 smd circle (at 0.4 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G12 smd circle (at 1.2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G13 smd circle (at 2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G14 smd circle (at 2.8 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G15 smd circle (at 3.6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G16 smd circle (at 4.4 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G17 smd circle (at 5.2 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad G18 smd circle (at 6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G19 smd circle (at 6.8 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad G20 smd circle (at 7.6 -2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H1 smd circle (at -7.6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H2 smd circle (at -6.8 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H3 smd circle (at -6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H4 smd circle (at -5.2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H5 smd circle (at -4.4 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H6 smd circle (at -3.6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H7 smd circle (at -2.8 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H8 smd circle (at -2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H9 smd circle (at -1.2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H10 smd circle (at -0.4 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H11 smd circle (at 0.4 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H12 smd circle (at 1.2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H13 smd circle (at 2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H14 smd circle (at 2.8 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H15 smd circle (at 3.6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad H16 smd circle (at 4.4 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H17 smd circle (at 5.2 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H18 smd circle (at 6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad H19 smd circle (at 6.8 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad H20 smd circle (at 7.6 -2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J1 smd circle (at -7.6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J2 smd circle (at -6.8 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J3 smd circle (at -6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J4 smd circle (at -5.2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J5 smd circle (at -4.4 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J6 smd circle (at -3.6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad J7 smd circle (at -2.8 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J8 smd circle (at -2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad J9 smd circle (at -1.2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J10 smd circle (at -0.4 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J11 smd circle (at 0.4 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J12 smd circle (at 1.2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J13 smd circle (at 2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad J14 smd circle (at 2.8 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad J15 smd circle (at 3.6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad J16 smd circle (at 4.4 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J17 smd circle (at 5.2 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J18 smd circle (at 6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J19 smd circle (at 6.8 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad J20 smd circle (at 7.6 -1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K1 smd circle (at -7.6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K2 smd circle (at -6.8 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K3 smd circle (at -6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K4 smd circle (at -5.2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K5 smd circle (at -4.4 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K6 smd circle (at -3.6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K7 smd circle (at -2.8 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K8 smd circle (at -2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad K9 smd circle (at -1.2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K10 smd circle (at -0.4 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K11 smd circle (at 0.4 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K12 smd circle (at 1.2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K13 smd circle (at 2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad K14 smd circle (at 2.8 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K15 smd circle (at 3.6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad K16 smd circle (at 4.4 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K17 smd circle (at 5.2 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K18 smd circle (at 6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K19 smd circle (at 6.8 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad K20 smd circle (at 7.6 -0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L1 smd circle (at -7.6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L2 smd circle (at -6.8 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L3 smd circle (at -6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L4 smd circle (at -5.2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L5 smd circle (at -4.4 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L6 smd circle (at -3.6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L7 smd circle (at -2.8 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L8 smd circle (at -2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L9 smd circle (at -1.2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad L10 smd circle (at -0.4 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad L11 smd circle (at 0.4 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad L12 smd circle (at 1.2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad L13 smd circle (at 2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L14 smd circle (at 2.8 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L15 smd circle (at 3.6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad L16 smd circle (at 4.4 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L17 smd circle (at 5.2 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L18 smd circle (at 6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L19 smd circle (at 6.8 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad L20 smd circle (at 7.6 0.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M1 smd circle (at -7.6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M2 smd circle (at -6.8 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M3 smd circle (at -6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M4 smd circle (at -5.2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M5 smd circle (at -4.4 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M6 smd circle (at -3.6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad M7 smd circle (at -2.8 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M8 smd circle (at -2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad M9 smd circle (at -1.2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M10 smd circle (at -0.4 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M11 smd circle (at 0.4 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M12 smd circle (at 1.2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M13 smd circle (at 2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad M14 smd circle (at 2.8 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M15 smd circle (at 3.6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad M16 smd circle (at 4.4 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad M17 smd circle (at 5.2 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M18 smd circle (at 6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M19 smd circle (at 6.8 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad M20 smd circle (at 7.6 1.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N1 smd circle (at -7.6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N2 smd circle (at -6.8 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N3 smd circle (at -6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N4 smd circle (at -5.2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N5 smd circle (at -4.4 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N6 smd circle (at -3.6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad N7 smd circle (at -2.8 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad N8 smd circle (at -2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N9 smd circle (at -1.2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N10 smd circle (at -0.4 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N11 smd circle (at 0.4 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N12 smd circle (at 1.2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N13 smd circle (at 2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad N14 smd circle (at 2.8 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad N15 smd circle (at 3.6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad N16 smd circle (at 4.4 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N17 smd circle (at 5.2 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N18 smd circle (at 6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N19 smd circle (at 6.8 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad N20 smd circle (at 7.6 2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P1 smd circle (at -7.6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P2 smd circle (at -6.8 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P3 smd circle (at -6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P4 smd circle (at -5.2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P5 smd circle (at -4.4 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P6 smd circle (at -3.6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad P7 smd circle (at -2.8 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P8 smd circle (at -2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P9 smd circle (at -1.2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad P10 smd circle (at -0.4 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad P11 smd circle (at 0.4 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P12 smd circle (at 1.2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P13 smd circle (at 2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P14 smd circle (at 2.8 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad P15 smd circle (at 3.6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 2 VCC))
(pad P16 smd circle (at 4.4 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P17 smd circle (at 5.2 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P18 smd circle (at 6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P19 smd circle (at 6.8 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad P20 smd circle (at 7.6 2.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R1 smd circle (at -7.6 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R2 smd circle (at -6.8 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R3 smd circle (at -6 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R4 smd circle (at -5.2 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R5 smd circle (at -4.4 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 3 /TDI))
(pad R16 smd circle (at 4.4 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R17 smd circle (at 5.2 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R18 smd circle (at 6 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad R19 smd circle (at 6.8 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad R20 smd circle (at 7.6 3.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T1 smd circle (at -7.6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T2 smd circle (at -6.8 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T3 smd circle (at -6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T4 smd circle (at -5.2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T5 smd circle (at -4.4 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 4 /TCK))
(pad T6 smd circle (at -3.6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad T7 smd circle (at -2.8 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad T8 smd circle (at -2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad T9 smd circle (at -1.2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad T10 smd circle (at -0.4 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad T11 smd circle (at 0.4 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T12 smd circle (at 1.2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T13 smd circle (at 2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T14 smd circle (at 2.8 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T15 smd circle (at 3.6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T16 smd circle (at 4.4 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T17 smd circle (at 5.2 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T18 smd circle (at 6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T19 smd circle (at 6.8 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad T20 smd circle (at 7.6 4.4) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U1 smd circle (at -7.6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U2 smd circle (at -6.8 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U3 smd circle (at -6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U4 smd circle (at -5.2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U5 smd circle (at -4.4 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 5 /TMS))
(pad U6 smd circle (at -3.6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U7 smd circle (at -2.8 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U8 smd circle (at -2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U9 smd circle (at -1.2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U10 smd circle (at -0.4 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U11 smd circle (at 0.4 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U12 smd circle (at 1.2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U13 smd circle (at 2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U14 smd circle (at 2.8 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad U15 smd circle (at 3.6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U16 smd circle (at 4.4 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U17 smd circle (at 5.2 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U18 smd circle (at 6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U19 smd circle (at 6.8 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad U20 smd circle (at 7.6 5.2) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V1 smd circle (at -7.6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V2 smd circle (at -6.8 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V3 smd circle (at -6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V4 smd circle (at -5.2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 6 /TDO))
(pad V5 smd circle (at -4.4 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V6 smd circle (at -3.6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V7 smd circle (at -2.8 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V8 smd circle (at -2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V9 smd circle (at -1.2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V10 smd circle (at -0.4 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V11 smd circle (at 0.4 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V12 smd circle (at 1.2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V13 smd circle (at 2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V14 smd circle (at 2.8 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V15 smd circle (at 3.6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V16 smd circle (at 4.4 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V17 smd circle (at 5.2 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V18 smd circle (at 6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad V19 smd circle (at 6.8 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad V20 smd circle (at 7.6 6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W1 smd circle (at -7.6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W2 smd circle (at -6.8 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W3 smd circle (at -6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W4 smd circle (at -5.2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W5 smd circle (at -4.4 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W6 smd circle (at -3.6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W7 smd circle (at -2.8 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W8 smd circle (at -2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W9 smd circle (at -1.2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W10 smd circle (at -0.4 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W11 smd circle (at 0.4 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W12 smd circle (at 1.2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W13 smd circle (at 2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W14 smd circle (at 2.8 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W15 smd circle (at 3.6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W16 smd circle (at 4.4 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W17 smd circle (at 5.2 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W18 smd circle (at 6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad W19 smd circle (at 6.8 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad W20 smd circle (at 7.6 6.8) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y2 smd circle (at -6.8 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y3 smd circle (at -6 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y5 smd circle (at -4.4 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y6 smd circle (at -3.6 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y7 smd circle (at -2.8 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y8 smd circle (at -2 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y11 smd circle (at 0.4 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y12 smd circle (at 1.2 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad Y14 smd circle (at 2.8 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y15 smd circle (at 3.6 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y16 smd circle (at 4.4 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y17 smd circle (at 5.2 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
(pad Y19 smd circle (at 6.8 7.6) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask))
)
(module SMD_Packages:SMD-1206_Pol (layer B.Cu) (tedit 0) (tstamp 56A9E514)
(at 120.442 87.127 90)
(path /56AA2821)
(attr smd)
(fp_text reference D4 (at 0 0 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 2A (at 0 0 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.54 1.143) (end -2.794 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 1.143) (end -2.794 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 -1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 -1.143) (end -0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 0.889 1.143) (end 2.54 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 1.143) (end 2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 -1.143) (end 0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -0.889 1.143) (end -2.54 1.143) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.651 0 90) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 9 "Net-(D4-Pad1)"))
screw holes proper spacing for M3
8 years ago
(pad 2 smd rect (at 1.651 0 90) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 7 +5V))
screw holes proper spacing for M3
8 years ago
(model SMD_Packages.3dshapes/SMD-1206_Pol.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module SMD_Packages:SMD-1206_Pol (layer B.Cu) (tedit 0) (tstamp 56A9E50E)
(at 117.642 87.025 270)
(path /56AA1324)
(attr smd)
(fp_text reference D3 (at 0 0 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 2A (at 0 0 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.54 1.143) (end -2.794 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 1.143) (end -2.794 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.794 -1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 1.143) (end -2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -2.54 -1.143) (end -0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 0.889 1.143) (end 2.54 1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 1.143) (end 2.54 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start 2.54 -1.143) (end 0.889 -1.143) (layer B.SilkS) (width 0.15))
(fp_line (start -0.889 1.143) (end -2.54 1.143) (layer B.SilkS) (width 0.15))
(pad 1 smd rect (at -1.651 0 270) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 7 +5V))
screw holes proper spacing for M3
8 years ago
(pad 2 smd rect (at 1.651 0 270) (size 1.524 2.032) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 8 /USB5V))
screw holes proper spacing for M3
8 years ago
(model SMD_Packages.3dshapes/SMD-1206_Pol.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module micro-sd:MicroSD_TF02D (layer F.Cu) (tedit 52721666) (tstamp 56A966AB)
shrinking the board
8 years ago
(at 95.8 90.03 90)
screw holes proper spacing for M3
8 years ago
(path /56ACBF19)
(fp_text reference SD1 (at 0 5.7 90) (layer F.SilkS)
(effects (font (size 0.59944 0.59944) (thickness 0.12446)))
)
(fp_text value SD_Card (at 0 4.35 90) (layer F.SilkS)
(effects (font (size 0.59944 0.59944) (thickness 0.12446)))
)
(fp_line (start 3.8 15.2) (end 3.8 16) (layer F.SilkS) (width 0.01016))
(fp_line (start 3.8 16) (end -7 16) (layer F.SilkS) (width 0.01016))
(fp_line (start -7 16) (end -7 15.2) (layer F.SilkS) (width 0.01016))
(fp_line (start 7 0) (end 7 15.2) (layer F.SilkS) (width 0.01016))
(fp_line (start 7 15.2) (end -7 15.2) (layer F.SilkS) (width 0.01016))
(fp_line (start -7 15.2) (end -7 0) (layer F.SilkS) (width 0.01016))
(fp_line (start -7 0) (end 7 0) (layer F.SilkS) (width 0.01016))
(pad 1 smd rect (at 1.94 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 34 /SD_3))
screw holes proper spacing for M3
8 years ago
(pad 2 smd rect (at 0.84 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 35 /MTMS))
(pad 3 smd rect (at -0.26 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -1.36 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask))
screw holes proper spacing for M3
8 years ago
(pad 5 smd rect (at -2.46 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 36 /MTCK))
(pad 6 smd rect (at -3.56 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask))
screw holes proper spacing for M3
8 years ago
(pad 7 smd rect (at -4.66 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 37 /MTDO))
screw holes proper spacing for M3
8 years ago
(pad 8 smd rect (at -5.76 11 90) (size 0.7 1.8) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 38 /MTDI))
screw holes proper spacing for M3
8 years ago
(pad S smd rect (at -5.05 0.4 90) (size 1.6 1.4) (layers F.Cu F.Paste F.Mask))
(pad S smd rect (at 0.75 0.4 90) (size 1.8 1.4) (layers F.Cu F.Paste F.Mask))
(pad G smd rect (at -7.45 13.55 90) (size 1.4 1.9) (layers F.Cu F.Paste F.Mask))
(pad G smd rect (at 6.6 14.55 90) (size 1.4 1.9) (layers F.Cu F.Paste F.Mask))
)
(module micro-hdmi-d:MICRO-HDMI-D (layer F.Cu) (tedit 53F70906) (tstamp 56A965BA)
shrinking the board
8 years ago
(at 113.15 62.69 180)
screw holes proper spacing for M3
8 years ago
(path /56ACD5D4)
(attr smd)
(fp_text reference GPDI1 (at -0.025 -3.125 180) (layer F.SilkS)
(effects (font (size 0.3 0.3) (thickness 0.075)))
)
(fp_text value MICRO-GPDI-D (at 0 -1.6 180) (layer F.SilkS)
(effects (font (size 0.3 0.3) (thickness 0.075)))
)
(fp_line (start -3.3 0) (end -3.3 0.7) (layer F.SilkS) (width 0.001))
(fp_line (start -3.3 0.7) (end 3.3 0.7) (layer F.SilkS) (width 0.001))
(fp_line (start 3.3 0.7) (end 3.3 0) (layer F.SilkS) (width 0.001))
(fp_line (start -3.3 0) (end -3.3 -6.8) (layer F.SilkS) (width 0.001))
(fp_line (start -3.3 -6.8) (end 3.3 -6.8) (layer F.SilkS) (width 0.001))
(fp_line (start 3.3 -6.8) (end 3.3 0) (layer F.SilkS) (width 0.001))
(fp_line (start 3.3 0) (end -3.3 0) (layer F.SilkS) (width 0.001))
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(pad 1 smd rect (at 1.8 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 1.4 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 1 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 0.6 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at 0.2 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at -0.2 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -0.6 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at -1 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at -1.4 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at -1.8 -6.475 180) (size 0.23 0.85) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 1.6 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 1.2 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 0.8 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 0.4 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 0 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -0.4 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at -0.8 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at -1.2 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at -1.6 -5.25 180) (size 0.23 1) (layers F.Cu F.Paste F.Mask))
screw holes proper spacing for M3
8 years ago
(pad SHD smd rect (at 3.45 -5.06 180) (size 2.4 1.38) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 41 "Net-(GPDI1-PadSHD)"))
screw holes proper spacing for M3
8 years ago
(pad SHD smd rect (at -3.45 -5.06 180) (size 2.4 1.38) (layers F.Cu F.Paste F.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 41 "Net-(GPDI1-PadSHD)"))
screw holes proper spacing for M3
8 years ago
(pad "" thru_hole oval (at -3.1 -1.7 180) (size 1.5 2.55) (drill oval 0.65 1.7) (layers *.Cu *.Mask F.SilkS))
(pad "" thru_hole oval (at 3.1 -1.7 180) (size 1.5 2.55) (drill oval 0.65 1.7) (layers *.Cu *.Mask F.SilkS))
)
(module ESP8266:ESP-12E (layer B.Cu) (tedit 559F8D21) (tstamp 56A95491)
shrinking the board
8 years ago
(at 96.64 83.01 270)
screw holes proper spacing for M3
8 years ago
(descr "Module, ESP-8266, ESP-12, 16 pad, SMD")
(tags "Module ESP-8266 ESP8266")
(path /56AC980A)
(fp_text reference U2 (at -2 2 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value ESP-12E (at 8 -1 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 16 8.4) (end 0 2.6) (layer B.CrtYd) (width 0.1524))
(fp_line (start 0 8.4) (end 16 2.6) (layer B.CrtYd) (width 0.1524))
(fp_text user "No Copper" (at 7.9 5.4 270) (layer B.CrtYd)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0 8.4) (end 0 2.6) (layer B.CrtYd) (width 0.1524))
(fp_line (start 0 2.6) (end 16 2.6) (layer B.CrtYd) (width 0.1524))
(fp_line (start 16 2.6) (end 16 8.4) (layer B.CrtYd) (width 0.1524))
(fp_line (start 16 8.4) (end 0 8.4) (layer B.CrtYd) (width 0.1524))
(fp_line (start 16 8.4) (end 16 -15.6) (layer B.Fab) (width 0.1524))
(fp_line (start 16 -15.6) (end 0 -15.6) (layer B.Fab) (width 0.1524))
(fp_line (start 0 -15.6) (end 0 8.4) (layer B.Fab) (width 0.1524))
(fp_line (start 0 8.4) (end 16 8.4) (layer B.Fab) (width 0.1524))
(pad 9 smd oval (at 2.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 37 /MTDO))
screw holes proper spacing for M3
8 years ago
(pad 10 smd oval (at 4.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 38 /MTDI))
screw holes proper spacing for M3
8 years ago
(pad 11 smd oval (at 6.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 34 /SD_3))
screw holes proper spacing for M3
8 years ago
(pad 12 smd oval (at 8.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 35 /MTMS))
screw holes proper spacing for M3
8 years ago
(pad 13 smd oval (at 10.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(net 36 /MTCK))
(pad 14 smd oval (at 12.99 -15.75 180) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 1 smd rect (at 0 0 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 2 smd oval (at 0 -2 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 3 smd oval (at 0 -4 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
screw holes proper spacing for M3
8 years ago
(pad 4 smd oval (at 0 -6 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
(net 3 /TDI))
(pad 5 smd oval (at 0 -8 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
(net 6 /TDO))
(pad 6 smd oval (at 0 -10 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
(net 4 /TCK))
(pad 7 smd oval (at 0 -12 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
(net 5 /TMS))
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(pad 8 smd oval (at 0 -14 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
screw holes proper spacing for M3
8 years ago
(pad 15 smd oval (at 16 -14 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(pad 16 smd oval (at 16 -12 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 17 smd oval (at 16 -10 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 18 smd oval (at 16 -8 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 19 smd oval (at 16 -6 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 20 smd oval (at 16 -4 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 21 smd oval (at 16 -2 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
(pad 22 smd oval (at 16 0 270) (size 2.4 1.1) (layers B.Cu B.Paste B.Mask))
screw holes proper spacing for M3
8 years ago
(model ${ESPLIB}/ESP8266.3dshapes/ESP-12.wrl
(at (xyz 0.04 0 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 0 0 0))
)
)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(module usb_otg:USB_Micro-B (layer F.Cu) (tedit 5543E447) (tstamp 58D43115)
shrinking the board
8 years ago
(at 135.39 65.31 180)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(descr "Micro USB Type B Receptacle")
(tags "USB USB_B USB_micro USB_OTG")
(path /58D432CE)
(attr smd)
(fp_text reference US1 (at 0 -3.24 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value USB_FTDI (at 0 5.01 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -4.6 -2.59) (end 4.6 -2.59) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.6 -2.59) (end 4.6 4.26) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.6 4.26) (end -4.6 4.26) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.6 4.26) (end -4.6 -2.59) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.35 4.03) (end 4.35 4.03) (layer F.SilkS) (width 0.12))
(fp_line (start -4.35 -2.38) (end 4.35 -2.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.35 -2.38) (end 4.35 4.03) (layer F.SilkS) (width 0.12))
(fp_line (start 4.35 2.8) (end -4.35 2.8) (layer F.SilkS) (width 0.12))
(fp_line (start -4.35 4.03) (end -4.35 -2.38) (layer F.SilkS) (width 0.12))
(pad 1 smd rect (at -1.3 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask)
(net 8 /USB5V))
(pad 2 smd rect (at -0.65 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 0 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 0.65 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 1.3 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 6 thru_hole oval (at -2.5 -1.35 270) (size 0.95 1.25) (drill oval 0.55 0.85) (layers *.Cu *.Mask)
(net 42 "Net-(US1-Pad6)"))
(pad 6 thru_hole oval (at 2.5 -1.35 270) (size 0.95 1.25) (drill oval 0.55 0.85) (layers *.Cu *.Mask)
(net 42 "Net-(US1-Pad6)"))
(pad 6 thru_hole oval (at -3.5 1.35 270) (size 1.55 1) (drill oval 1.15 0.5) (layers *.Cu *.Mask)
(net 42 "Net-(US1-Pad6)"))
(pad 6 thru_hole oval (at 3.5 1.35 270) (size 1.55 1) (drill oval 1.15 0.5) (layers *.Cu *.Mask)
(net 42 "Net-(US1-Pad6)"))
)
(module usb_otg:USB_Micro-B (layer F.Cu) (tedit 5543E447) (tstamp 58D43122)
shrinking the board
8 years ago
(at 157.6 65.31 180)
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
(descr "Micro USB Type B Receptacle")
(tags "USB USB_B USB_micro USB_OTG")
(path /58D4378B)
(attr smd)
(fp_text reference US2 (at 0 -3.24 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value USB_FPGA (at 0 5.01 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -4.6 -2.59) (end 4.6 -2.59) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.6 -2.59) (end 4.6 4.26) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.6 4.26) (end -4.6 4.26) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.6 4.26) (end -4.6 -2.59) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.35 4.03) (end 4.35 4.03) (layer F.SilkS) (width 0.12))
(fp_line (start -4.35 -2.38) (end 4.35 -2.38) (layer F.SilkS) (width 0.12))
(fp_line (start 4.35 -2.38) (end 4.35 4.03) (layer F.SilkS) (width 0.12))
(fp_line (start 4.35 2.8) (end -4.35 2.8) (layer F.SilkS) (width 0.12))
(fp_line (start -4.35 4.03) (end -4.35 -2.38) (layer F.SilkS) (width 0.12))
(pad 1 smd rect (at -1.3 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(D4-Pad1)"))
(pad 2 smd rect (at -0.65 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 0 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 0.65 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 1.3 -1.35 270) (size 1.35 0.4) (layers F.Cu F.Paste F.Mask)
(net 1 GND))
(pad 6 thru_hole oval (at -2.5 -1.35 270) (size 0.95 1.25) (drill oval 0.55 0.85) (layers *.Cu *.Mask)
(net 43 "Net-(US2-Pad6)"))
(pad 6 thru_hole oval (at 2.5 -1.35 270) (size 0.95 1.25) (drill oval 0.55 0.85) (layers *.Cu *.Mask)
(net 43 "Net-(US2-Pad6)"))
(pad 6 thru_hole oval (at -3.5 1.35 270) (size 1.55 1) (drill oval 1.15 0.5) (layers *.Cu *.Mask)
(net 43 "Net-(US2-Pad6)"))
(pad 6 thru_hole oval (at 3.5 1.35 270) (size 1.55 1) (drill oval 1.15 0.5) (layers *.Cu *.Mask)
(net 43 "Net-(US2-Pad6)"))
)
chip name edited on JTAG to be the same as all units
8 years ago
(module Socket_Strips:Socket_Strip_Angled_2x32 (layer F.Cu) (tedit 0) (tstamp 58D4E99D)
(at 96.64 104.6)
(descr "Through hole socket strip")
(tags "socket strip")
(path /56AC389C/58D39D36)
(fp_text reference J1 (at 0 -4.6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_02X32 (at 0 -2.6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.75 -1.35) (end -1.75 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 80.5 -1.35) (end 80.5 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 -1.35) (end 80.5 -1.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 13.15) (end 80.5 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 80.01 3.81) (end 80.01 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 77.47 3.81) (end 80.01 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 77.47 12.64) (end 80.01 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 80.01 12.64) (end 80.01 3.81) (layer F.SilkS) (width 0.15))
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(fp_line (start 31.75 3.81) (end 31.75 12.64) (layer F.SilkS) (width 0.15))
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(fp_line (start 1.27 12.64) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
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(fp_line (start 3.81 3.81) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 3.81) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.15) (end -1.55 -1.15) (layer F.SilkS) (width 0.15))
(fp_line (start -1.55 -1.15) (end -1.55 0) (layer F.SilkS) (width 0.15))
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(fp_line (start -1.27 12.64) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 12.64) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 10 /gpio/IN5V))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 11 /gpio/OUT5V))
(pad 3 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 5 thru_hole oval (at 5.08 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 12 /gpio/P5))
(pad 6 thru_hole oval (at 5.08 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 13 /gpio/P6))
(pad 7 thru_hole oval (at 7.62 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 14 /gpio/P7))
(pad 8 thru_hole oval (at 7.62 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 15 /gpio/P8))
(pad 9 thru_hole oval (at 10.16 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 39 /gpio/P9))
(pad 10 thru_hole oval (at 10.16 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 40 /gpio/P10))
(pad 11 thru_hole oval (at 12.7 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 16 /gpio/P11))
(pad 12 thru_hole oval (at 12.7 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 17 /gpio/P12))
(pad 13 thru_hole oval (at 15.24 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 18 /gpio/P13))
(pad 14 thru_hole oval (at 15.24 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 19 /gpio/P14))
(pad 15 thru_hole oval (at 17.78 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 44 /gpio/P15))
(pad 16 thru_hole oval (at 17.78 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 45 /gpio/P16))
(pad 17 thru_hole oval (at 20.32 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 20 /gpio/P17))
(pad 18 thru_hole oval (at 20.32 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 21 /gpio/P18))
(pad 19 thru_hole oval (at 22.86 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 22 /gpio/P19))
(pad 20 thru_hole oval (at 22.86 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 23 /gpio/P20))
(pad 21 thru_hole oval (at 25.4 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 24 /gpio/P21))
(pad 22 thru_hole oval (at 25.4 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 25 /gpio/P22))
(pad 23 thru_hole oval (at 27.94 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 26 /gpio/P23))
(pad 24 thru_hole oval (at 27.94 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 27 /gpio/P24))
(pad 25 thru_hole oval (at 30.48 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 28 /gpio/P25))
(pad 26 thru_hole oval (at 30.48 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 29 /gpio/P26))
(pad 27 thru_hole oval (at 33.02 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 30 /gpio/P27))
(pad 28 thru_hole oval (at 33.02 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 31 /gpio/P28))
(pad 29 thru_hole oval (at 35.56 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 32 /gpio/P29))
(pad 30 thru_hole oval (at 35.56 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 33 /gpio/P30))
(pad 31 thru_hole oval (at 38.1 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 46 /gpio/P31))
(pad 32 thru_hole oval (at 38.1 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 47 /gpio/P32))
(pad 33 thru_hole oval (at 40.64 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 48 /gpio/P33))
(pad 34 thru_hole oval (at 40.64 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 49 /gpio/P34))
(pad 35 thru_hole oval (at 43.18 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 50 /gpio/P35))
(pad 36 thru_hole oval (at 43.18 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 51 /gpio/P36))
(pad 37 thru_hole oval (at 45.72 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 52 /gpio/P37))
(pad 38 thru_hole oval (at 45.72 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 53 /gpio/P38))
(pad 39 thru_hole oval (at 48.26 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 54 /gpio/P39))
(pad 40 thru_hole oval (at 48.26 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 55 /gpio/P40))
(pad 41 thru_hole oval (at 50.8 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 56 /gpio/P41))
(pad 42 thru_hole oval (at 50.8 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 57 /gpio/P42))
(pad 43 thru_hole oval (at 53.34 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 58 /gpio/P43))
(pad 44 thru_hole oval (at 53.34 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 59 /gpio/P44))
(pad 45 thru_hole oval (at 55.88 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 60 /gpio/P45))
(pad 46 thru_hole oval (at 55.88 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 61 /gpio/P46))
(pad 47 thru_hole oval (at 58.42 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 62 /gpio/P47))
(pad 48 thru_hole oval (at 58.42 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 63 /gpio/P48))
(pad 49 thru_hole oval (at 60.96 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 64 /gpio/P49))
(pad 50 thru_hole oval (at 60.96 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 65 /gpio/P50))
(pad 51 thru_hole oval (at 63.5 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 66 /gpio/P51))
(pad 52 thru_hole oval (at 63.5 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 67 /gpio/P52))
(pad 53 thru_hole oval (at 66.04 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 68 /gpio/P53))
(pad 54 thru_hole oval (at 66.04 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 69 /gpio/P54))
(pad 55 thru_hole oval (at 68.58 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 70 /gpio/P55))
(pad 56 thru_hole oval (at 68.58 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 71 /gpio/P56))
(pad 57 thru_hole oval (at 71.12 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 72 /gpio/P57))
(pad 58 thru_hole oval (at 71.12 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 73 /gpio/P58))
(pad 59 thru_hole oval (at 73.66 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 74 /gpio/P59))
(pad 60 thru_hole oval (at 73.66 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 75 /gpio/P60))
(pad 61 thru_hole oval (at 76.2 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 62 thru_hole oval (at 76.2 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 63 thru_hole oval (at 78.74 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 64 thru_hole oval (at 78.74 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(model Socket_Strips.3dshapes/Socket_Strip_Angled_2x32.wrl
(at (xyz 1.55 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 180))
)
)
(module Socket_Strips:Socket_Strip_Angled_2x15 (layer F.Cu) (tedit 0) (tstamp 58D4E9E0)
shrinking the board
8 years ago
(at 172.84 99.52 90)
chip name edited on JTAG to be the same as all units
8 years ago
(descr "Through hole socket strip")
(tags "socket strip")
(path /56AC389C/58D3A6D6)
shrinking the board
8 years ago
(fp_text reference J3 (at 0 -4.6 90) (layer F.SilkS)
chip name edited on JTAG to be the same as all units
8 years ago
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_02X15 (at 0 -2.6 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.75 -1.35) (end -1.75 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 37.35 -1.35) (end 37.35 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 -1.35) (end 37.35 -1.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 13.15) (end 37.35 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.51 12.64) (end 16.51 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 13.97 12.64) (end 16.51 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 13.97 3.81) (end 16.51 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 3.81) (end 16.51 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 19.05 3.81) (end 19.05 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 3.81) (end 19.05 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 12.64) (end 19.05 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 19.05 12.64) (end 19.05 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 21.59 12.64) (end 21.59 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 19.05 12.64) (end 21.59 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 19.05 3.81) (end 21.59 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 21.59 3.81) (end 21.59 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 24.13 3.81) (end 24.13 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 21.59 3.81) (end 24.13 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 21.59 12.64) (end 24.13 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 24.13 12.64) (end 24.13 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 26.67 3.81) (end 26.67 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 24.13 3.81) (end 26.67 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 24.13 12.64) (end 26.67 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 26.67 12.64) (end 26.67 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 29.21 12.64) (end 29.21 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 26.67 12.64) (end 29.21 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 26.67 3.81) (end 29.21 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 29.21 3.81) (end 29.21 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 31.75 3.81) (end 31.75 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 29.21 3.81) (end 31.75 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 29.21 12.64) (end 31.75 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 31.75 12.64) (end 31.75 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 34.29 12.64) (end 34.29 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 31.75 12.64) (end 34.29 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 31.75 3.81) (end 34.29 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 34.29 3.81) (end 34.29 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 36.83 3.81) (end 36.83 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 34.29 3.81) (end 36.83 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 34.29 12.64) (end 36.83 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 36.83 12.64) (end 36.83 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 13.97 12.64) (end 13.97 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 12.64) (end 13.97 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 3.81) (end 13.97 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 13.97 3.81) (end 13.97 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 3.81) (end 11.43 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 3.81) (end 11.43 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 12.64) (end 11.43 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 12.64) (end 11.43 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 12.64) (end 8.89 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 12.64) (end 8.89 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 3.81) (end 8.89 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 3.81) (end 8.89 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 3.81) (end 6.35 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 3.81) (end 6.35 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 12.64) (end 6.35 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 12.64) (end 6.35 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 12.64) (end 3.81 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 12.64) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 3.81) (end 3.81 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 3.81) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 3.81) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.15) (end -1.55 -1.15) (layer F.SilkS) (width 0.15))
(fp_line (start -1.55 -1.15) (end -1.55 0) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 3.81) (end -1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 12.64) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 12.64) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 3 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 5 thru_hole oval (at 5.08 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 5.08 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at 7.62 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 7.62 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 10.16 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 10 thru_hole oval (at 10.16 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 11 thru_hole oval (at 12.7 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 12 thru_hole oval (at 12.7 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 13 thru_hole oval (at 15.24 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 14 thru_hole oval (at 15.24 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 15 thru_hole oval (at 17.78 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 16 thru_hole oval (at 17.78 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 17 thru_hole oval (at 20.32 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 18 thru_hole oval (at 20.32 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 19 thru_hole oval (at 22.86 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 20 thru_hole oval (at 22.86 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 21 thru_hole oval (at 25.4 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 22 thru_hole oval (at 25.4 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 23 thru_hole oval (at 27.94 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 24 thru_hole oval (at 27.94 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 25 thru_hole oval (at 30.48 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 26 thru_hole oval (at 30.48 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 27 thru_hole oval (at 33.02 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 28 thru_hole oval (at 33.02 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 29 thru_hole oval (at 35.56 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 30 thru_hole oval (at 35.56 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(model Socket_Strips.3dshapes/Socket_Strip_Angled_2x15.wrl
(at (xyz 0.7 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 180))
)
)
shrinking the board
8 years ago
(module Socket_Strips:Socket_Strip_Angled_2x06 (layer F.Cu) (tedit 0) (tstamp 58D4F693)
(at 99.18 63.96 270)
(descr "Through hole socket strip")
(tags "socket strip")
(path /56AC389C/58D50D04)
(fp_text reference J2 (at 0 -4.6 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_02X06 (at 0 -2.6 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.75 -1.35) (end -1.75 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 14.45 -1.35) (end 14.45 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 -1.35) (end 14.45 -1.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 13.15) (end 14.45 13.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 13.97 12.64) (end 13.97 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 12.64) (end 13.97 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 3.81) (end 13.97 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 13.97 3.81) (end 13.97 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 3.81) (end 11.43 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 3.81) (end 11.43 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 12.64) (end 11.43 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 11.43 12.64) (end 11.43 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 12.64) (end 8.89 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 12.64) (end 8.89 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 3.81) (end 8.89 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 8.89 3.81) (end 8.89 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 3.81) (end 6.35 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 3.81) (end 6.35 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 12.64) (end 6.35 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 6.35 12.64) (end 6.35 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 12.64) (end 3.81 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 12.64) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 3.81) (end 3.81 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 3.81 3.81) (end 3.81 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 3.81) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.15) (end -1.55 -1.15) (layer F.SilkS) (width 0.15))
(fp_line (start -1.55 -1.15) (end -1.55 0) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 3.81) (end -1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start -1.27 12.64) (end 1.27 12.64) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 12.64) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 2 VCC))
(pad 3 thru_hole oval (at 2.54 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 4 thru_hole oval (at 2.54 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask)
(net 1 GND))
(pad 5 thru_hole oval (at 5.08 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 5.08 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at 7.62 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 7.62 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 10.16 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 10 thru_hole oval (at 10.16 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 11 thru_hole oval (at 12.7 0 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(pad 12 thru_hole oval (at 12.7 2.54 270) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask))
(model Socket_Strips.3dshapes/Socket_Strip_Angled_2x06.wrl
(at (xyz 0.25 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 180))
)
)
(dimension 48.26 (width 0.3) (layer Eco2.User)
(gr_text "48,260 mm" (at 77.51 85.55 90) (layer Eco2.User)
screw holes proper spacing for M3
8 years ago
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
shrinking the board
8 years ago
(feature1 (pts (xy 94.1 61.42) (xy 76.16 61.42)))
(feature2 (pts (xy 94.1 109.68) (xy 76.16 109.68)))
(crossbar (pts (xy 78.86 109.68) (xy 78.86 61.42)))
(arrow1a (pts (xy 78.86 61.42) (xy 79.446421 62.546504)))
(arrow1b (pts (xy 78.86 61.42) (xy 78.273579 62.546504)))
(arrow2a (pts (xy 78.86 109.68) (xy 79.446421 108.553496)))
(arrow2b (pts (xy 78.86 109.68) (xy 78.273579 108.553496)))
screw holes proper spacing for M3
8 years ago
)
shrinking the board
8 years ago
(dimension 83.82 (width 0.3) (layer Eco2.User)
(gr_text "83,820 mm" (at 136.01 44.83) (layer Eco2.User)
screw holes proper spacing for M3
8 years ago
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
shrinking the board
8 years ago
(feature1 (pts (xy 94.1 61.42) (xy 94.1 43.48)))
(feature2 (pts (xy 177.92 61.42) (xy 177.92 43.48)))
(crossbar (pts (xy 177.92 46.18) (xy 94.1 46.18)))
(arrow1a (pts (xy 94.1 46.18) (xy 95.226504 45.593579)))
(arrow1b (pts (xy 94.1 46.18) (xy 95.226504 46.766421)))
(arrow2a (pts (xy 177.92 46.18) (xy 176.793496 45.593579)))
(arrow2b (pts (xy 177.92 46.18) (xy 176.793496 46.766421)))
screw holes proper spacing for M3
8 years ago
)
changing BANK0 (Unit A) shematic symbol and adding BANK1 (Unit B)
8 years ago
(gr_circle (center 90.29 57.61) (end 91.89 57.61) (layer Edge.Cuts) (width 0.2) (tstamp 58D43D22))
reverting layout back to original, just a bit larger board that fits M3 screws
8 years ago
(gr_arc (start 90.29 57.61) (end 86.48 57.61) (angle 90) (layer Edge.Cuts) (width 0.3))
(gr_circle (center 90.29 57.61) (end 87.29 57.61) (layer Dwgs.User) (width 0.2) (tstamp 58D43D12))
(gr_arc (start 181.73 57.61) (end 181.73 53.8) (angle 90) (layer Edge.Cuts) (width 0.3))
(gr_circle (center 181.73 57.61) (end 178.73 57.61) (layer Dwgs.User) (width 0.2) (tstamp 58D43B0E))
(gr_circle (center 181.73 57.61) (end 183.33 57.61) (layer Edge.Cuts) (width 0.3) (tstamp 58D43B08))
(gr_arc (start 181.73 105.87) (end 185.54 105.87) (angle 90) (layer Edge.Cuts) (width 0.3))
(gr_arc (start 90.29 105.87) (end 90.29 109.68) (angle 90) (layer Edge.Cuts) (width 0.3))
(gr_circle (center 181.73 105.87) (end 183.33 105.87) (layer Edge.Cuts) (width 0.3))
(gr_circle (center 181.73 105.87) (end 178.73 105.87) (layer Dwgs.User) (width 0.2))
(gr_circle (center 90.29 105.87) (end 87.29 105.87) (layer Dwgs.User) (width 0.2))
changing BANK0 (Unit A) shematic symbol and adding BANK1 (Unit B)
8 years ago
(gr_circle (center 90.29 105.87) (end 91.89 105.87) (layer Edge.Cuts) (width 0.2))
reverting layout back to original, just a bit larger board that fits M3 screws
8 years ago
(dimension 91.44 (width 0.3) (layer Eco2.User)
shrinking the board
8 years ago
(gr_text "91,440 mm" (at 136.01 34.67) (layer Eco2.User) (tstamp 58D43A2D)
screw holes proper spacing for M3
8 years ago
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
shrinking the board
8 years ago
(feature1 (pts (xy 181.73 57.61) (xy 181.73 33.32)))
(feature2 (pts (xy 90.29 57.61) (xy 90.29 33.32)))
(crossbar (pts (xy 90.29 36.02) (xy 181.73 36.02)))
(arrow1a (pts (xy 181.73 36.02) (xy 180.603496 36.606421)))
(arrow1b (pts (xy 181.73 36.02) (xy 180.603496 35.433579)))
(arrow2a (pts (xy 90.29 36.02) (xy 91.416504 36.606421)))
(arrow2b (pts (xy 90.29 36.02) (xy 91.416504 35.433579)))
screw holes proper spacing for M3
8 years ago
)
reverting layout back to original, just a bit larger board that fits M3 screws
8 years ago
(dimension 48.26 (width 0.3) (layer Eco2.User)
shrinking the board
8 years ago
(gr_text "48,260 mm" (at 69.89 81.74 90) (layer Eco2.User) (tstamp 58D3B9B8)
screw holes proper spacing for M3
8 years ago
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
shrinking the board
8 years ago
(feature1 (pts (xy 90.29 57.61) (xy 68.54 57.61)))
(feature2 (pts (xy 90.29 105.87) (xy 68.54 105.87)))
(crossbar (pts (xy 71.24 105.87) (xy 71.24 57.61)))
(arrow1a (pts (xy 71.24 57.61) (xy 71.826421 58.736504)))
(arrow1b (pts (xy 71.24 57.61) (xy 70.653579 58.736504)))
(arrow2a (pts (xy 71.24 105.87) (xy 71.826421 104.743496)))
(arrow2b (pts (xy 71.24 105.87) (xy 70.653579 104.743496)))
screw holes proper spacing for M3
8 years ago
)
shrinking the board
8 years ago
(gr_line (start 94.1 61.42) (end 94.1 109.68) (layer Edge.Cuts) (width 0.3))
(gr_line (start 177.92 61.42) (end 94.1 61.42) (layer Edge.Cuts) (width 0.3))
(gr_line (start 177.92 109.68) (end 177.92 61.42) (layer Edge.Cuts) (width 0.3))
(gr_line (start 94.1 109.68) (end 177.92 109.68) (layer Edge.Cuts) (width 0.3))
screw holes proper spacing for M3
8 years ago
chip name edited on JTAG to be the same as all units
8 years ago
(segment (start 131.485886 80.794114) (end 131.485886 94.44) (width 0.25) (layer In1.Cu) (net 26))
(segment (start 124.58 104.6) (end 124.58 101.345886) (width 0.25) (layer In1.Cu) (net 26))
(segment (start 124.58 101.345886) (end 131.485886 94.44) (width 0.25) (layer In1.Cu) (net 26))
(segment (start 132.28 80) (end 131.485886 80.794114) (width 0.25) (layer In1.Cu) (net 26))
(segment (start 132.68 79.6) (end 132.28 80) (width 0.25) (layer F.Cu) (net 26))
(via micro (at 132.28 80) (size 0.3) (drill 0.1) (layers F.Cu In1.Cu) (net 26))
FPGA aligned to 0.2 mm raster and one trace routead as example using Ctrl-V for micro-via
8 years ago
screw holes proper spacing for M3
8 years ago
)