disallow micro via

normal via routing example

ulx3s.kicad_pcb

@@ -6,7 +6,7 @@
     (area 93.949999 61.269999 178.070001 109.830001)
     (thickness 1.6)
     (drawings 10)
-    (tracks 1)
+    (tracks 7)
     (zones 0)
     (modules 74)
     (nets 100)
@@ -48,11 +48,11 @@
     (edge_width 0.2)
     (via_size 0.6)
     (via_drill 0.4)
-    (via_min_size 0.4)
+    (via_min_size 0.2)
-    (via_min_drill 0.3)
+    (via_min_drill 0.1)
     (uvia_size 0.3)
     (uvia_drill 0.1)
-    (uvias_allowed yes)
+    (uvias_allowed no)
     (uvia_min_size 0.2)
     (uvia_min_drill 0.1)
     (pcb_text_width 0.3)
@@ -281,10 +281,6 @@
     (add_net BTN_L)
     (add_net BTN_R)
     (add_net BTN_U)
-    (add_net JTAG_TCK)
-    (add_net JTAG_TDI)
-    (add_net JTAG_TDO)
-    (add_net JTAG_TMS)
     (add_net "Net-(BTN1-Pad1)")
     (add_net "Net-(D9-Pad1)")
     (add_net "Net-(L1-Pad1)")
@@ -304,11 +300,15 @@
   (net_class BGA ""
     (clearance 0.1)
     (trace_width 0.2)
-    (via_dia 0.6)
+    (via_dia 0.33)
-    (via_drill 0.4)
+    (via_drill 0.15)
     (uvia_dia 0.3)
     (uvia_drill 0.1)
     (add_net GND)
+    (add_net JTAG_TCK)
+    (add_net JTAG_TDI)
+    (add_net JTAG_TDO)
+    (add_net JTAG_TMS)
   )
 
   (module Keystone_3000_1x12mm-CoinCell:Keystone_3000_1x12mm-CoinCell (layer B.Cu) (tedit 58D7D5B5) (tstamp 58D7ADD9)
@@ -4087,5 +4087,11 @@
   (gr_line (start 94.1 109.68) (end 177.92 109.68) (layer Edge.Cuts) (width 0.3))
 
   (segment (start 159.05 83.772) (end 158.95 83.772) (width 0.25) (layer B.Cu) (net 0))
+  (segment (start 102.26 81.74) (end 102.26 83.78) (width 0.2) (layer B.Cu) (net 89))
+  (via (at 102.26 83.78) (size 0.33) (drill 0.15) (layers F.Cu B.Cu) (net 89))
+  (segment (start 107.28 88.8) (end 102.26 83.78) (width 0.2) (layer In1.Cu) (net 89))
+  (segment (start 130.68 88.8) (end 107.28 88.8) (width 0.2) (layer In1.Cu) (net 89))
+  (segment (start 131.08 88.4) (end 130.68 88.8) (width 0.2) (layer F.Cu) (net 89))
+  (via (at 130.68 88.8) (size 0.33) (drill 0.15) (layers F.Cu B.Cu) (net 89))
 
 )

ulx3s.kicad_pcb-bak

@@ -65,7 +65,7 @@
     (pad_to_mask_clearance 0.2)
     (aux_axis_origin 82.67 62.69)
     (grid_origin 86.48 79.2)
-    (visible_elements 7FFFBFFF)
+    (visible_elements 7FFFFFFF)
     (pcbplotparams
       (layerselection 0x010f0_80000007)
       (usegerberextensions false)