schematics: note on Flash over JTAG programming

pull/3/head
Emard 7 years ago
parent 2d1bec3e88
commit 31814ddf66

@ -489,4 +489,6 @@ F 4 "www.mouser.com" H 6400 2850 60 0001 C CNN "Distributor1_URL"
7 6400 2850 7 6400 2850
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Text Notes 1500 3500 0 60 ~ 0
For programming Flash thru JTAG see\nLattice FPGA-TN-02050
$EndSCHEMATC $EndSCHEMATC

@ -100,7 +100,7 @@ Text GLabel 4050 3600 0 60 Input ~ 0
SD_D0 SD_D0
Text GLabel 4050 3700 0 60 Input ~ 0 Text GLabel 4050 3700 0 60 Input ~ 0
SD_D1 SD_D1
Text Notes 4150 4600 0 60 ~ 0 Text Notes 4200 4750 0 60 ~ 0
minimum pins for compatible mode\nSD_CLK, SD_CMD, SD_D0, SD_D3 minimum pins for compatible mode\nSD_CLK, SD_CMD, SD_D0, SD_D3
$Comp $Comp
L R R38 L R R38
@ -172,23 +172,19 @@ SDcard connected to\nBANK6 on "usb" sheet
$Comp $Comp
L GND #PWR? L GND #PWR?
U 1 1 5A2A690D U 1 1 5A2A690D
P 4900 4150 P 4900 4250
F 0 "#PWR?" H 4900 3900 50 0001 C CNN F 0 "#PWR?" H 4900 4000 50 0001 C CNN
F 1 "GND" H 4900 4000 50 0000 C CNN F 1 "GND" H 4900 4100 50 0000 C CNN
F 2 "" H 4900 4150 50 0000 C CNN F 2 "" H 4900 4250 50 0000 C CNN
F 3 "" H 4900 4150 50 0000 C CNN F 3 "" H 4900 4250 50 0000 C CNN
1 4900 4150 1 4900 4250
1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 5A2A6924
P 5000 4150
F 0 "#PWR?" H 5000 3900 50 0001 C CNN
F 1 "GND" H 5000 4000 50 0000 C CNN
F 2 "" H 5000 4150 50 0000 C CNN
F 3 "" H 5000 4150 50 0000 C CNN
1 5000 4150
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
Wire Wire Line
4900 4150 4900 4250
Wire Wire Line
4900 4200 5000 4200
Wire Wire Line
5000 4200 5000 4150
Connection ~ 4900 4200
$EndSCHEMATC $EndSCHEMATC

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