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schematics v1.8.7: reconnecting SD card for 180 deg rotation

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pull/3/head
Emard 7 years ago
parent 5263a5dff5
commit 3d6aac6f9c
5 changed files with 38 additions and 21 deletions
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5
gpdi.bak
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@ -245,8 +245,6 @@ F 0 "R23" V 5130 5200 50 0000 C CNN
F 1 "3.3k" V 5050 5200 50 0000 C CNN F 1 "3.3k" V 5050 5200 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 4980 5200 50 0001 C CNN F 2 "Resistor_SMD:R_0603_1608Metric" V 4980 5200 50 0001 C CNN
F 3 "" H 5050 5200 50 0000 C CNN F 3 "" H 5050 5200 50 0000 C CNN
F 4 "www.yageo.com" V 5050 5200 50 0001 C CNN "MFG1_URL"
F 5 "RC0603FR-072K2L" V 5050 5200 50 0001 C CNN "MPN"
1 5050 5200 1 5050 5200
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
@ -258,9 +256,6 @@ F 0 "R22" V 4980 5200 50 0000 C CNN
F 1 "3.3k" V 4900 5200 50 0000 C CNN F 1 "3.3k" V 4900 5200 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 4830 5200 50 0001 C CNN F 2 "Resistor_SMD:R_0603_1608Metric" V 4830 5200 50 0001 C CNN
F 3 "" H 4900 5200 50 0000 C CNN F 3 "" H 4900 5200 50 0000 C CNN
F 4 "RC0603FR-072K2L" V 4900 5200 50 0001 C CNN "MPN"
F 5 "603-RC0603FR-072K2L" V 4900 5200 50 0001 C CNN "Mouser"
F 6 "311-2.2KLDCT-ND" V 4900 5200 50 0001 C CNN "Digikey"
1 4900 5200 1 4900 5200
1 0 0 -1 1 0 0 -1
$EndComp $EndComp

2
ulx3s.bak
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@ -7,7 +7,7 @@ encoding utf-8
Sheet 1 11 Sheet 1 11
Title "ULX3S" Title "ULX3S"
Date "" Date ""
Rev "1.8.6" Rev "1.8.7"
Comp "FER+RIZ+RADIONA" Comp "FER+RIZ+RADIONA"
Comment1 "Root sheet" Comment1 "Root sheet"
Comment2 "" Comment2 ""

2
ulx3s.sch
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@ -7,7 +7,7 @@ encoding utf-8
Sheet 1 11 Sheet 1 11
Title "ULX3S" Title "ULX3S"
Date "" Date ""
Rev "1.8.6" Rev "1.8.7"
Comp "FER+RIZ+RADIONA" Comp "FER+RIZ+RADIONA"
Comment1 "Root sheet" Comment1 "Root sheet"
Comment2 "" Comment2 ""

26
usb.bak
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@ -324,17 +324,15 @@ Text GLabel 8650 2850 0 60 Input ~ 0
OLED_DC OLED_DC
Text GLabel 8650 2650 0 60 Input ~ 0 Text GLabel 8650 2650 0 60 Input ~ 0
OLED_CS OLED_CS
Text GLabel 8650 1850 0 60 Input ~ 0 Text GLabel 8650 1550 0 60 Input ~ 0
SD_D0 SD_D0
Text GLabel 10150 1750 2 60 Input ~ 0 Text GLabel 10150 1750 2 60 Input ~ 0
SD_D1
Text GLabel 10150 1850 2 60 Input ~ 0
SD_D2 SD_D2
Text GLabel 8650 1750 0 60 Input ~ 0 Text GLabel 8650 1850 0 60 Input ~ 0
SD_D3 SD_D3
Text GLabel 8650 1350 0 60 Input ~ 0 Text GLabel 8650 1350 0 60 Input ~ 0
SD_CLK SD_CLK
Text GLabel 8650 1550 0 60 Input ~ 0 Text GLabel 10150 1850 2 60 Input ~ 0
SD_CMD SD_CMD
Text GLabel 10150 2150 2 60 Input ~ 0 Text GLabel 10150 2150 2 60 Input ~ 0
SD_WP SD_WP
@ -731,9 +729,9 @@ Text GLabel 8650 2150 0 60 Input ~ 0
WIFI_GPIO5 WIFI_GPIO5
Text GLabel 8650 2450 0 60 Input ~ 0 Text GLabel 8650 2450 0 60 Input ~ 0
WIFI_GPIO17 WIFI_GPIO17
Text Notes 7500 1400 0 60 ~ 0 Text Notes 6850 1400 0 60 ~ 0
SD_D2 v1.7 SD_D2 v1.7
Text Notes 10600 1900 0 60 ~ 0 Text Notes 11150 1900 0 60 ~ 0
SD_CLK v1.7 SD_CLK v1.7
Text GLabel 1600 4650 0 60 Input ~ 0 Text GLabel 1600 4650 0 60 Input ~ 0
USB_FPGA_PULL_D+ USB_FPGA_PULL_D+
@ -885,4 +883,18 @@ F 4 "1N4148WS" H 1950 5450 50 0001 C CNN "MPN"
$EndComp $EndComp
Text Label 1850 2650 0 60 ~ 0 Text Label 1850 2650 0 60 ~ 0
US2VBUS US2VBUS
Text Notes 10600 1900 0 60 ~ 0
SD_D2 v1.8
Text Notes 10600 1800 0 60 ~ 0
SD_D1 v1.8
Text Notes 7450 1400 0 60 ~ 0
SD_CLK v1.8
Text Notes 7450 1600 0 60 ~ 0
SD_CMD v1.8
Text Notes 7450 1800 0 60 ~ 0
SD_D3 v1.8
Text Notes 7450 1900 0 60 ~ 0
SD_D0 v1.8
Text GLabel 8650 1750 0 60 Input ~ 0
SD_D1
$EndSCHEMATC $EndSCHEMATC

24
usb.sch
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@ -324,17 +324,15 @@ Text GLabel 8650 2850 0 60 Input ~ 0
OLED_DC OLED_DC
Text GLabel 8650 2650 0 60 Input ~ 0 Text GLabel 8650 2650 0 60 Input ~ 0
OLED_CS OLED_CS
Text GLabel 8650 1850 0 60 Input ~ 0 Text GLabel 8650 1550 0 60 Input ~ 0
SD_D0 SD_D0
Text GLabel 10150 1750 2 60 Input ~ 0 Text GLabel 10150 1750 2 60 Input ~ 0
SD_D1
Text GLabel 10150 1850 2 60 Input ~ 0
SD_D2 SD_D2
Text GLabel 8650 1750 0 60 Input ~ 0 Text GLabel 8650 1850 0 60 Input ~ 0
SD_D3 SD_D3
Text GLabel 8650 1350 0 60 Input ~ 0 Text GLabel 8650 1350 0 60 Input ~ 0
SD_CLK SD_CLK
Text GLabel 8650 1550 0 60 Input ~ 0 Text GLabel 10150 1850 2 60 Input ~ 0
SD_CMD SD_CMD
Text GLabel 10150 2150 2 60 Input ~ 0 Text GLabel 10150 2150 2 60 Input ~ 0
SD_WP SD_WP
@ -731,9 +729,9 @@ Text GLabel 8650 2150 0 60 Input ~ 0
WIFI_GPIO5 WIFI_GPIO5
Text GLabel 8650 2450 0 60 Input ~ 0 Text GLabel 8650 2450 0 60 Input ~ 0
WIFI_GPIO17 WIFI_GPIO17
Text Notes 7500 1400 0 60 ~ 0 Text Notes 7450 1400 0 60 ~ 0
SD_D2 v1.7 SD_D2 v1.7
Text Notes 10600 1900 0 60 ~ 0 Text Notes 11150 1900 0 60 ~ 0
SD_CLK v1.7 SD_CLK v1.7
Text GLabel 1600 4650 0 60 Input ~ 0 Text GLabel 1600 4650 0 60 Input ~ 0
USB_FPGA_PULL_D+ USB_FPGA_PULL_D+
@ -885,4 +883,16 @@ F 4 "1N4148WS" H 1950 5450 50 0001 C CNN "MPN"
$EndComp $EndComp
Text Label 1850 2650 0 60 ~ 0 Text Label 1850 2650 0 60 ~ 0
US2VBUS US2VBUS
Text Notes 10600 1900 0 60 ~ 0
SD_D2 v1.8
Text Notes 10600 1800 0 60 ~ 0
SD_D1 v1.8
Text Notes 7450 1600 0 60 ~ 0
SD_CMD v1.8
Text Notes 7450 1800 0 60 ~ 0
SD_D3 v1.8
Text Notes 7450 1900 0 60 ~ 0
SD_D0 v1.8
Text GLabel 8650 1750 0 60 Input ~ 0
SD_D1
$EndSCHEMATC $EndSCHEMATC

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