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@ -69,7 +69,7 @@ section (thicker power lines, separately routed feedback)
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[x] Compile differential GPDI output
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[ ] Connect more lines from ESP-32 to FPGA
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[x] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[ ] FPGA USB add 22ohm+3.6Vzener
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[ ] FPGA USB add 27 ohm + 3.6 V zener
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[ ] Symmetrically place USB connectors left-right
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[ ] Jumpers to switch 2.5V/3.3V for left IO banks
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[x] External JTAG header
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