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@ -66,3 +66,4 @@ section (thicker power lines, separately routed feedback)
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[ ] compile a f32c bitstream using the schematics
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[ ] compile a f32c bitstream using the schematics
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[ ] connect more lines from ESP-32 to FPGA
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[ ] connect more lines from ESP-32 to FPGA
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[ ] connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[ ] connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[ ] Jumpers to switch 2.5V/3.3V for left IO banks
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