connecting all BTNs except power BTN

8 years ago · aeaf64f99c
parent 1204ae1172
commit aeaf64f99c
4 changed files with 3206 additions and 2953 deletions
--- a/flash.sch
+++ b/flash.sch
@ -458,11 +458,11 @@ Text GLabel 5650 2150 0    60   Input ~ 0
 BTN_F1
 Text GLabel 7150 2150 2    60   Input ~ 0
 BTN_F2
-Text GLabel 5650 2250 0    60   Input ~ 0
+Text GLabel 5650 2350 0    60   Input ~ 0
 BTN_U
 Text GLabel 7150 2250 2    60   Input ~ 0
 BTN_D
-Text GLabel 5650 2350 0    60   Input ~ 0
+Text GLabel 5650 2250 0    60   Input ~ 0
 BTN_L
 Text GLabel 7150 2350 2    60   Input ~ 0
 BTN_R
--- a/power.bak
+++ b/power.bak
@ -844,7 +844,7 @@ F 3 "" H 2700 5750 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 Text Notes 5600 6400 0    60   ~ 0
-Important:\nPlace voltage feedback RC network\nclose to FPGA. Placement of \nSMPS chip and L doesn't matter.
+Important:\nPlace voltage feedback and filter \nRC network close to FPGA. Position of \nSMPS chip and L doesn't matter.\n
 $Comp
 L D D13
 U 1 1 58DA2DA9
--- a/ulx3s.kicad_pcb
+++ b/ulx3s.kicad_pcb
--- a/ulx3s.kicad_pcb-bak
+++ b/ulx3s.kicad_pcb-bak