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board production rules for oshpart

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pull/3/head
davor 8 years ago
parent 1c5b8a64a3
commit dd597e7b49
3 changed files with 68 additions and 58 deletions
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4
doc/board-production-rules.txt
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@ -0,0 +1,4 @@
oshpark
The minimum specs for 4 layer orders are
5 mil (0.127 mm) traces with 5 mil (0.127 mm) spacing,
and 10 mil (0.254 mm) drills with 4 mil (0.1 mm) annular rings.

21
ulx3s.kicad_pcb
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@ -3,10 +3,10 @@
(general (general
(links 561) (links 561)
(no_connects 561) (no_connects 561)
(area 93.949999 61.269999 188.230001 112.370001) (area 71.010001 43.48 197.645001 118.805339)
(thickness 1.6) (thickness 1.6)
(drawings 6) (drawings 6)
(tracks 0) (tracks 2)
(zones 0) (zones 0)
(modules 112) (modules 112)
(nets 206) (nets 206)
@ -43,13 +43,13 @@
(trace_clearance 0.2) (trace_clearance 0.2)
(zone_clearance 0.508) (zone_clearance 0.508)
(zone_45_only no) (zone_45_only no)
(trace_min 0.2) (trace_min 0.127)
(segment_width 0.2) (segment_width 0.2)
(edge_width 0.2) (edge_width 0.2)
(via_size 0.6) (via_size 0.6)
(via_drill 0.4) (via_drill 0.4)
(via_min_size 0.2) (via_min_size 0.45)
(via_min_drill 0.1) (via_min_drill 0.254)
(uvia_size 0.3) (uvia_size 0.3)
(uvia_drill 0.1) (uvia_drill 0.1)
(uvias_allowed no) (uvias_allowed no)
@ -314,7 +314,6 @@
(add_net /analog/AUDIO_L) (add_net /analog/AUDIO_L)
(add_net /analog/AUDIO_R) (add_net /analog/AUDIO_R)
(add_net /blinkey/BTNPU) (add_net /blinkey/BTNPU)
(add_net /gpdi/CLK_25MHz)
(add_net /gpdi/VREF2) (add_net /gpdi/VREF2)
(add_net /gpio/IN5V) (add_net /gpio/IN5V)
(add_net /gpio/OUT5V) (add_net /gpio/OUT5V)
@ -347,10 +346,10 @@
) )
(net_class BGA "" (net_class BGA ""
(clearance 0.1) (clearance 0.13)
(trace_width 0.2) (trace_width 0.2)
(via_dia 0.33) (via_dia 0.45)
(via_drill 0.15) (via_drill 0.254)
(uvia_dia 0.3) (uvia_dia 0.3)
(uvia_drill 0.1) (uvia_drill 0.1)
(add_net /flash/FLASH_MISO) (add_net /flash/FLASH_MISO)
@ -362,6 +361,7 @@
(add_net /flash/FPGA_DONE) (add_net /flash/FPGA_DONE)
(add_net /flash/FPGA_INITN) (add_net /flash/FPGA_INITN)
(add_net /flash/FPGA_PROGRAMN) (add_net /flash/FPGA_PROGRAMN)
(add_net /gpdi/CLK_25MHz)
(add_net /gpio/A10) (add_net /gpio/A10)
(add_net /gpio/A11) (add_net /gpio/A11)
(add_net /gpio/A12) (add_net /gpio/A12)
@ -5784,4 +5784,7 @@
(gr_line (start 188.08 112.22) (end 188.08 61.42) (layer Edge.Cuts) (width 0.3)) (gr_line (start 188.08 112.22) (end 188.08 61.42) (layer Edge.Cuts) (width 0.3))
(gr_line (start 94.1 112.22) (end 188.08 112.22) (layer Edge.Cuts) (width 0.3)) (gr_line (start 94.1 112.22) (end 188.08 112.22) (layer Edge.Cuts) (width 0.3))
(segment (start 129.48 82.8) (end 129.52853 82.8) (width 0.2) (layer F.Cu) (net 117))
(segment (start 129.48 82.8) (end 129.52146 82.8) (width 0.2) (layer F.Cu) (net 117))
) )

101
ulx3s.kicad_pcb-bak
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@ -3,10 +3,10 @@
(general (general
(links 561) (links 561)
(no_connects 561) (no_connects 561)
(area 93.949999 61.269999 188.230001 112.370001) (area 71.010001 43.48 197.645001 118.805339)
(thickness 1.6) (thickness 1.6)
(drawings 6) (drawings 6)
(tracks 0) (tracks 2)
(zones 0) (zones 0)
(modules 112) (modules 112)
(nets 206) (nets 206)
@ -43,13 +43,13 @@
(trace_clearance 0.2) (trace_clearance 0.2)
(zone_clearance 0.508) (zone_clearance 0.508)
(zone_45_only no) (zone_45_only no)
(trace_min 0.2) (trace_min 0.127)
(segment_width 0.2) (segment_width 0.2)
(edge_width 0.2) (edge_width 0.2)
(via_size 0.6) (via_size 0.6)
(via_drill 0.4) (via_drill 0.4)
(via_min_size 0.2) (via_min_size 0.45)
(via_min_drill 0.1) (via_min_drill 0.254)
(uvia_size 0.3) (uvia_size 0.3)
(uvia_drill 0.1) (uvia_drill 0.1)
(uvias_allowed no) (uvias_allowed no)
@ -314,7 +314,6 @@
(add_net /analog/AUDIO_L) (add_net /analog/AUDIO_L)
(add_net /analog/AUDIO_R) (add_net /analog/AUDIO_R)
(add_net /blinkey/BTNPU) (add_net /blinkey/BTNPU)
(add_net /gpdi/CLK_25MHz)
(add_net /gpdi/VREF2) (add_net /gpdi/VREF2)
(add_net /gpio/IN5V) (add_net /gpio/IN5V)
(add_net /gpio/OUT5V) (add_net /gpio/OUT5V)
@ -347,10 +346,10 @@
) )
(net_class BGA "" (net_class BGA ""
(clearance 0.1) (clearance 0.13)
(trace_width 0.2) (trace_width 0.2)
(via_dia 0.33) (via_dia 0.45)
(via_drill 0.15) (via_drill 0.254)
(uvia_dia 0.3) (uvia_dia 0.3)
(uvia_drill 0.1) (uvia_drill 0.1)
(add_net /flash/FLASH_MISO) (add_net /flash/FLASH_MISO)
@ -362,6 +361,7 @@
(add_net /flash/FPGA_DONE) (add_net /flash/FPGA_DONE)
(add_net /flash/FPGA_INITN) (add_net /flash/FPGA_INITN)
(add_net /flash/FPGA_PROGRAMN) (add_net /flash/FPGA_PROGRAMN)
(add_net /gpdi/CLK_25MHz)
(add_net /gpio/A10) (add_net /gpio/A10)
(add_net /gpio/A11) (add_net /gpio/A11)
(add_net /gpio/A12) (add_net /gpio/A12)
@ -5678,46 +5678,6 @@
) )
) )
(module Crystals:Crystal_SMD_7050_4Pads (layer B.Cu) (tedit 57404CCC) (tstamp 58EDF62C)
(at 109.34 71.58)
(descr "Ceramic SMD crystal, 7.0x5.0mm, 4 Pads")
(tags "crystal oscillator quartz SMD SMT 7050")
(path /58D686D9/58EDFF94)
(attr smd)
(fp_text reference Y1 (at 0 4) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value FNETHE025 (at 0 -4) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -3.5 -2.5) (end -3.5 2.5) (layer B.Fab) (width 0.15))
(fp_line (start 3.5 -2.5) (end -3.5 -2.5) (layer B.Fab) (width 0.15))
(fp_line (start 3.5 2.5) (end 3.5 -2.5) (layer B.Fab) (width 0.15))
(fp_line (start -3.5 2.5) (end 3.5 2.5) (layer B.Fab) (width 0.15))
(fp_line (start -3.6 -2.3) (end -4.15 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 -2.6) (end 3.6 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 2.6) (end 3.6 2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 2.6) (end -3.6 2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -2.6) (end -3.6 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -2.6) (end 3.6 -2.6) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -0.2) (end -4.15 -0.2) (layer B.SilkS) (width 0.15))
(fp_line (start -4.75 3.1) (end -4.75 -3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start 4.75 3.1) (end -4.75 3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.6 2.6) (end 3.6 2.6) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 -0.2) (end 3.6 0.2) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -0.2) (end -3.6 0.2) (layer B.SilkS) (width 0.15))
(fp_line (start 4.75 -3.1) (end -4.75 -3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start 4.75 3.1) (end 4.75 -3.1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at -3.15 -1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 3 smd rect (at 3.15 -1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 205 /gpdi/CLK_25MHz))
(pad 2 smd rect (at 3.15 1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 3 smd rect (at -3.15 1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 205 /gpdi/CLK_25MHz))
)
(module abs25:Crystal_SMD_ABS25 (layer B.Cu) (tedit 58D83518) (tstamp 58EDF633) (module abs25:Crystal_SMD_ABS25 (layer B.Cu) (tedit 58D83518) (tstamp 58EDF633)
(at 175.38 98.25) (at 175.38 98.25)
(descr "Abracon ABS25 Plastic SMD Crystal http://www.abracon.com/Resonators/abs25.pdf") (descr "Abracon ABS25 Plastic SMD Crystal http://www.abracon.com/Resonators/abs25.pdf")
@ -5755,6 +5715,46 @@
(net 34 /power/OSCI_32k)) (net 34 /power/OSCI_32k))
) )
(module oscxo:Crystal_SMD_7050_4Pads (layer B.Cu) (tedit 58EE0D05) (tstamp 58EE1137)
(at 111.88 71.58)
(descr "Crystal oscillator, 7.0x5.0mm, 4 Pads")
(tags "crystal oscillator quartz SMD SMT 7050")
(path /58D686D9/58EDFF94)
(attr smd)
(fp_text reference Y1 (at 0 4) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value FNETHE025 (at 0 -4) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -3.5 -2.5) (end -3.5 2.5) (layer B.Fab) (width 0.15))
(fp_line (start 3.5 -2.5) (end -3.5 -2.5) (layer B.Fab) (width 0.15))
(fp_line (start 3.5 2.5) (end 3.5 -2.5) (layer B.Fab) (width 0.15))
(fp_line (start -3.5 2.5) (end 3.5 2.5) (layer B.Fab) (width 0.15))
(fp_line (start -3.6 -2.3) (end -4.15 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 -2.6) (end 3.6 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 2.6) (end 3.6 2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 2.6) (end -3.6 2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -2.6) (end -3.6 -2.3) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -2.6) (end 3.6 -2.6) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -0.2) (end -4.15 -0.2) (layer B.SilkS) (width 0.15))
(fp_line (start -4.75 3.1) (end -4.75 -3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start 4.75 3.1) (end -4.75 3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.6 2.6) (end 3.6 2.6) (layer B.SilkS) (width 0.15))
(fp_line (start 3.6 -0.2) (end 3.6 0.2) (layer B.SilkS) (width 0.15))
(fp_line (start -3.6 -0.2) (end -3.6 0.2) (layer B.SilkS) (width 0.15))
(fp_line (start 4.75 -3.1) (end -4.75 -3.1) (layer B.CrtYd) (width 0.05))
(fp_line (start 4.75 3.1) (end 4.75 -3.1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at -3.15 -1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
(pad 2 smd rect (at 3.15 -1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 1 GND))
(pad 3 smd rect (at 3.15 1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 205 /gpdi/CLK_25MHz))
(pad 4 smd rect (at -3.15 1.25) (size 2.2 1.4) (layers B.Cu B.Paste B.Mask)
(net 5 +3V3))
)
(dimension 50.8 (width 0.3) (layer Eco2.User) (dimension 50.8 (width 0.3) (layer Eco2.User)
(gr_text "50,800 mm" (at 77.51 86.82 90) (layer Eco2.User) (gr_text "50,800 mm" (at 77.51 86.82 90) (layer Eco2.User)
(effects (font (size 1.5 1.5) (thickness 0.3))) (effects (font (size 1.5 1.5) (thickness 0.3)))
@ -5784,4 +5784,7 @@
(gr_line (start 188.08 112.22) (end 188.08 61.42) (layer Edge.Cuts) (width 0.3)) (gr_line (start 188.08 112.22) (end 188.08 61.42) (layer Edge.Cuts) (width 0.3))
(gr_line (start 94.1 112.22) (end 188.08 112.22) (layer Edge.Cuts) (width 0.3)) (gr_line (start 94.1 112.22) (end 188.08 112.22) (layer Edge.Cuts) (width 0.3))
(segment (start 129.48 82.8) (end 129.52853 82.8) (width 0.2) (layer F.Cu) (net 117))
(segment (start 129.48 82.8) (end 129.52146 82.8) (width 0.2) (layer F.Cu) (net 117))
) )

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