80294dfd4a
gerbers update
6 years ago
797d383599
PCB: trac cosmetix
6 years ago
ab295886d4
gerbers update
6 years ago
807be26e47
PCB: trac cosmetix
6 years ago
1a6df7e37e
gerbers update
6 years ago
28caee6000
PCB: trac cosmetix
6 years ago
79e99bf474
schematics: Mark as NC all BGA pins which are NC in 12F FPGA chip.
...
So those pins can be recognized in PCB as having no net name.
Those pins may have use on other chips 25F, 45F or 85F but we
won't used those pins because the buard is designed to for
work for all.
6 years ago
7ba680435a
gerbers update
6 years ago
acb0a3d0ab
PCB: trac cosmetix
6 years ago
b9dbffc24d
gerbers update
6 years ago
6a0c0ab47f
PCB: silkscreen block for handwritten notes
6 years ago
4a0309ef58
gerbers update
6 years ago
3021028ff5
PCB: trac cosmetix, routing BTN_R around to allow more BGA GND VIAs
6 years ago
d99b484728
gerbers: trac cosmetix
6 years ago
6d07a69129
PCB: trac cosmetix
6 years ago
685dbb01b3
gerbers update
6 years ago
893f23e27c
PCB: add more VIAs under BGA
6 years ago
d159872c39
pic v2.0.9
6 years ago
854f71bdda
PCB: FPGA again set as visible in 3D view
6 years ago
ca1d1bb1b4
gerbers v2.0.9
6 years ago
676837ef3d
PCB v2.0.9: trac/via cosmetix
6 years ago
f7dbe05a86
gerbers v2.0.8
6 years ago
91b435bdfa
PCB v2.0.8: removing fill GND top layer under BGA, trac cosmetix
6 years ago
728c4c63db
gerbers update
6 years ago
ca91d6bb34
PCB: reducing copper traces on top layer under BGA to 0.127 mm
6 years ago
628cfc36a0
gerbers update
6 years ago
26ea73e434
PCB: trac cosmetix
6 years ago
8254f6b1bf
pic v2.0.7
6 years ago
42cd91b0af
gerbers v2.0.7
6 years ago
3aa8344fe6
PCB v2.0.7
6 years ago
1899935077
schematics v2.0.7
6 years ago
6c4868a752
PCB: thicker under SD card 0.127 -> 0.19 mm
6 years ago
f18467c4a7
PCB: thicker USB_FPGA 0.127 -> 0.19 mm
6 years ago
89a8f56097
PCB: thicker GPN0-27 0.127 -> 0.19 mm
6 years ago
d6ccd6d60c
PCB: thicker to LEDs 0.127 -> 0.19 mm
6 years ago
2709e5df41
PCB: thicker traces (0.5 mm) to 2.54 mm connectors J1, J2, SDRAM 0.127 -> 0.19 mm
6 years ago
5e928d9e7f
schematics: change P-N in GPN11,12,13 for easier wifi routing
6 years ago
f3cd6335a2
PCB: enlarging BGA vias to 0.419 mm, DRC passed, need trac cosmetix
6 years ago
c98ea8dcdc
PCB: net class enlarged VIA diameter 0.4 -> 0.419 mm
6 years ago
8d85bf2d47
PCB: thinner BGA traces 0.19 -> 0.127 mm (5 mil), DRC passed
6 years ago
c942bf5a60
PCB: aligning VIAs under BGA to 0.4 mm raster
6 years ago
ac500e7ca9
BGA pads increased to 0.4mm but VIAs remain the same
6 years ago
acaf1fc5d3
readme: todo enlarge BGA pads align VIA to BGA raster
6 years ago
8dd4311d72
PCB: reduced clearance 0.127->0.1 mm to accept BGA slightly larger pads
6 years ago
186c9793f8
BGA footprint with design rules according to Lattice Recommendations
6 years ago
321f82dc86
BGA layout updated with refernce to lattice document
...
TN1074: PCB Layout Recommendations for BGA Packages
6 years ago
5a6e8fd91d
BOM update
7 years ago
0131ac8882
PCB: C60 (B0 debouncer) smaller footprint 0805->0603, trac cosmetix
7 years ago
d0e01b6022
schematics: C60 (B0 debouncer) smaller capacitor 2.2uF->220nF, note PWRBTn to PROGRAMN
7 years ago
889a2f59da
readme update
7 years ago
Emard