200 Commits (3a7636f4b5dc6ab3dbe68e52711c078b2dc0bec3)

 

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Author	SHA1	Message	Date
davor	3a7636f4b5	update production helper files	7 years ago
davor	cb7be3d517	update drill file (merge both hole types into single drill files)	7 years ago
davor	302cb6d867	small update for gerber readme	7 years ago
davor	b17b4a481b	helper files for submission to seeedstudio production	7 years ago
davor	962282a4ac	updated gerber drill file	7 years ago
davor	9ddf4f58e5	delete old drill files	7 years ago
davor	92f4d68d07	gerber update	7 years ago
davor	c381c4c5c4	small PCB optimizations	7 years ago
davor	a6cf1f07ac	deleting old gerbers	7 years ago
davor	1f60f95a71	compatible OLED models: SSD1306 or SSD1331	7 years ago
davor	ea97d2573c	schematics.pdf	7 years ago
davor	bb82a9ac86	gerbers update	7 years ago
Emard	28c4106026	J2 GPIO: routed in the purple plane only	7 years ago
Emard	aabd353e71	J1 GPIO: grouping lines on purple plane	7 years ago
Emard	752eddee0e	J1 routed using only purple plane, (yellow plane made free)	7 years ago
davor	1e5e0b01a6	connecting JTAG lines to FTDI serial lines RI DCD CTS DSR ... as those pins are by default inputs and can be reconfigured as outputs similar but not identical pinout as the one that works from ujprog CBUS used to force-wakeup of the board from sleep state 2 LEDs to CBUS pins to display usb enumeration and activity status	7 years ago
davor	57fa143c11	connecting 2.5V and 3.3V sources to BGA planes	7 years ago
davor	4a0cc08307	connecting 1.2V core voltage, solving FPGA voltage plane, ... still too thin wire leading to SMPS supply	7 years ago
davor	ad274f07a2	recommendations for BGA381 4-layer PCB layout	7 years ago
Emard	5e953da6b9	connecting required pins for WiFi programming	7 years ago
Emard	5432fd6540	connecting clock and ftdi USB	7 years ago
Emard	4c13f262e8	connecting FTDI TXD/RXD	7 years ago
Emard	092e601af1	connecting LEDs	7 years ago
Emard	364957f9e0	connecting OLED	7 years ago
Emard	feb31c8f87	moving inner layer routes away from BGA	7 years ago
Emard	24c52062fa	moving routes under BGA out of inner layers	7 years ago
Emard	6e2e5f8c39	moving routing out of inner layers under BGA to allow ... larger copper fill zone for power supply	7 years ago
davor	3a9160cb16	scrapping current routing, placing power supply on copper zones under the BGA	7 years ago
davor	21aa552e1a	placing copper fill zones for power supply by the book ... similar to TN1074	7 years ago
Emard	37f7a62a25	reducing minimal drill size to 0.2 mm as ... recommended in lattice BGA guide. Seeedstudio meets this capabilities OSHpark doesn't	7 years ago
Emard	1392c5aa2b	how to route BGA	7 years ago
Emard	8061b47da8	moving some resistor near flash chip	7 years ago
Emard	b12f1b64a6	routing spi flash lines	7 years ago
Emard	820f30f598	routing JTAG	7 years ago
davor	3a079bd1d2	moving some resistor closer to ftdi	7 years ago
davor	48f79d581b	reordering PCB elements to simplify or shorten routes	7 years ago
Emard	6e48d42150	fully routed GPIO	7 years ago
davor	dcc2d375ea	routing additional pins to J2 GPIO. 2 differential pairs left to route	7 years ago
davor	9f0d9c46a7	routing half of J2 gpio	7 years ago
Emard	e30bbeea40	routing 4 GPIO on J2	7 years ago
Emard	48dc148919	manually routing J1 differential	7 years ago
Emard	9050eefd6e	update fill zone	7 years ago
Davor	55ecd6c1c2	update 3D view top	7 years ago
Davor	56e8ad2710	update 3D view pictures	7 years ago
Davor	3446afcc08	optimizing PCB component placement ... and audio bit ordering	7 years ago
Davor	19b884baef	using corrected schem symbol, reordering pins	7 years ago
Davor	a4b74230d3	fixing errors in schem symbol BANK6	7 years ago
Davor	af58a36fbd	delete old FPGA schem. symbol component from the library	7 years ago
Davor	39dce76f0a	use new schem symbol	7 years ago
Davor	e5f97e1897	schematic symbol FPGA: mark bank physical location ... on the floorplan	7 years ago