4d3828764b
tidying up routes
8 years ago
5f589c33f4
USB directly to FPGA for possible USB1.1 core
8 years ago
236f63488a
DIP SWITCH routed
8 years ago
6d14ed8ff0
Placing DIP switch, but not yet connecting it to FPGA
8 years ago
37bb008e24
ADC connecting REF+/REF- and SPI
8 years ago
2ca8acc32d
ADC chip moved on top layer.
...
Connecting 8 analog lines to J2
and remaining VCC/GND
8 years ago
32836831ae
i2c of RTC connected to GPDI i2c
8 years ago
ee20b46f6d
connecting ADC substrate pad to GND
8 years ago
a0d3693b66
moving ADC chip near J2, better possibility to get routed
8 years ago
851f2a0162
optimizing PCB lines for +5V
8 years ago
2153a220a0
schematic symbol for ADC MAX11123
...
small PCB traces cleanup
ADC chip placed on PCB but connected only to GND
8 years ago
be09416928
Add 27 ohm resistors in series with FTDI USB and readme update
8 years ago
278ac6b341
2.2uF for ESP-32 and gerber update
8 years ago
81b3ea5da0
adding minimal set of 3 2.2uF capacitor for 1.2V, 2.5V and 3.3V
8 years ago
96fabee1bc
Moving C18 away from battery
8 years ago
a11072b4e4
beautifying routes of LEDs and moving oscillator under the LEDs
8 years ago
ee7d266543
Resistors for LEDs
8 years ago
18aef04f2c
JTAG header
8 years ago
238ad770ce
moving USB LEDs on TOP layer
8 years ago
dcbf46dff2
optimizing PCB
8 years ago
34c4e9d7f3
increasing power via diameter
8 years ago
b7500cc477
increasing thickness of power traces, moving clock
...
to a bank which is always at 3.3V
8 years ago
57fdb7743e
1mm thick 5V line
8 years ago
76542e7630
moving FTDI USB on top
8 years ago
1a122bfc67
fully routed
8 years ago
dbf4b92a22
audio DAC routed
8 years ago
23b588ff16
Routing... 4 routes remaining
8 years ago
f036dae0fd
tidying up some traces, nothing important
8 years ago
f7f305ad0d
tidying up SDRAM connections. Trace lengths unequal,
...
expected about 0.1 ns time difference
8 years ago
20cbbc4ef9
continue routing PCB
8 years ago
eb3fc2ec70
connecting some GNDs and GNDing unnamed shield pads on USB connectors
8 years ago
b1718ae700
thick power lines
8 years ago
7d0fc68da0
connecting 2.5V
8 years ago
108abc3158
connecting 3.3V and 1.2V
8 years ago
ecc772b518
optimizing wakeup network
...
moving SMPS power supply networks
1.2V supply moved to the right
8 years ago
aeaf64f99c
connecting all BTNs except power BTN
8 years ago
dcbfda0556
Run DRC to update cupper fill zones
8 years ago
9d6f8bf493
improving SD card power supply and replacing with
...
suitable schematic symbol for micro SD card (was normal SD card)
8 years ago
2426a9f7e7
DRC rerun
8 years ago
5590ba802d
optimizing routing for SD and FTDI
8 years ago
c381c4c5c4
small PCB optimizations
8 years ago
1f60f95a71
compatible OLED models: SSD1306 or SSD1331
8 years ago
28c4106026
J2 GPIO: routed in the purple plane only
8 years ago
aabd353e71
J1 GPIO: grouping lines on purple plane
8 years ago
752eddee0e
J1 routed using only purple plane, (yellow plane made free)
8 years ago
1e5e0b01a6
connecting JTAG lines to FTDI serial lines RI DCD CTS DSR
...
as those pins are by default inputs and can be reconfigured as outputs
similar but not identical pinout as the one that works from ujprog
CBUS used to force-wakeup of the board from sleep state
2 LEDs to CBUS pins to display usb enumeration and activity status
8 years ago
57fa143c11
connecting 2.5V and 3.3V sources to BGA planes
8 years ago
4a0cc08307
connecting 1.2V core voltage, solving FPGA voltage plane,
...
still too thin wire leading to SMPS supply
8 years ago
5e953da6b9
connecting required pins for WiFi programming
8 years ago
5432fd6540
connecting clock and ftdi USB
8 years ago
Emard