PCB for ULX3S FPGA R&D board. Fork Sand fork of https://github.com/emard/ulx3s https://www.forksand.com/
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moving silkscreen values and references out of BGA pads
7 years ago
doc ADC datasheets 8 years ago
footprints connecting ADC substrate pad to GND 8 years ago
pic update jpeg's 7 years ago
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.gitignore use new footprint for crystal oscillator 8 years ago
README.md readme 7 years ago
analog.bak DIP SWITCH routed 8 years ago
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blinkey.bak DIP SWITCH routed 8 years ago
blinkey.sch DIP SWITCH routed 8 years ago
flash.bak DIP SWITCH routed 8 years ago
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fp-lib-table use new footprint for crystal oscillator 8 years ago
gpdi.bak DIP SWITCH routed 8 years ago
gpdi.sch Placing DIP switch, but not yet connecting it to FPGA 8 years ago
gpio.bak USB directly to FPGA for possible USB1.1 core 8 years ago
gpio.sch DIP SWITCH routed 8 years ago
power.bak ADC chip moved on top layer. 8 years ago
power.sch i2c of RTC connected to GPDI i2c 8 years ago
ram.bak DIP SWITCH routed 8 years ago
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sdcard.bak DIP SWITCH routed 8 years ago
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ulx3s-cache.lib connecting ADC substrate pad to GND 8 years ago
ulx3s-rescue.lib updating pins for BANK1 (still incomplete) 8 years ago
ulx3s.bak schematic symbol for ADC MAX11123 8 years ago
ulx3s.kicad_pcb moving silkscreen values and references out of BGA pads 7 years ago
ulx3s.kicad_pcb-bak moving silkscreen values and references out of BGA pads 7 years ago
ulx3s.pro schematic symbol for ADC MAX11123 8 years ago
ulx3s.sch schematic symbol for ADC MAX11123 8 years ago
usb.bak USB directly to FPGA for possible USB1.1 core 8 years ago
usb.sch USB directly to FPGA for possible USB1.1 core 8 years ago
wifi.bak DIP SWITCH routed 8 years ago
wifi.sch Placing DIP switch, but not yet connecting it to FPGA 8 years ago

README.md

ULX3S PCB

This is work-in-progress place for putting some wishes of a small (94x51 mm) FPGA board.

Instead of describing in written, it is better explained when drawn in kicad:

kicad ulx3s.pro

Schematics is mostly complete. PCB routing is complete, but needs improvement mainly for the power supply.

3D preview

TOP BOTTOM

Features

FPGA: Lattice ECP5 LFE5U-25F-6BG381C

USB: FTDI FT231XS (1Mbit JTAG and 3Mbit usbserial)

GPIO: All differential, PMOD-friendly

RAM: 32MB SDRAM MT48LC16M16

Flash: 8MB SPI flash S25FL164 for FPGA config

Storage: Micro-SD slot

LEDs: 10 (8 blink-LEDs, 2 USB leds)

Buttons: 6 (4 direction and 2 fire buttons)

Audio: 3.5 mm stereo jack

Video: GPDI connector with 3.3V-5V I2C bidirectional level shifter

Display: placeholder for 0.96-1.3" SPI OLED COLOR or B/W

WiFi+bluetooth: placeholder for ESP-32 (JTAG and serial over WiFi possible)

Power: 3 Switching voltage regulators: 1.2V, 2.5V, 3.3V

Low power sleep: RTC clock wakeup, quartz and battery

GPDI is General Purpose Differential Interface, Electrically LVDS, mostly TMDS tolerant female receptacle more-or-less compatible with digital monitors/TVs

Todo

Finish routing and especially improve Power section (thicker power lines, separately routed feedback)

2.54 mm external JTAG header

[ ] Silkscreen Double outline for BGA chip
[ ] Do not write silkscreen over the pads
[ ] Values on silkscreen
[x] Resistors for LEDs
[x] Move USB LEDs from bottom to top side
[ ] Improve SDRAM routing - use VIAs for closest pins
[x] Increase thickness of power lines (5V, 3.3V, 2.5V)
[x] Compile a f32c bitstream using the schematics
[x] Compile differential GPDI output
[ ] Connect more lines from ESP-32 to FPGA
[x] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
[ ] FPGA USB add 27 ohm + 3.6 V zener
[ ] Symmetrically place USB connectors left-right 
[ ] Jumpers to switch 2.5V/3.3V for left IO banks
[x] External JTAG header
[ ] Move WiFi Disable jumper above the buttons
[x] Sprinkle 2.2F capacitors on power lines
[ ] Spice simulation of power-up/shutdown network
[ ] Dedicated antenna pin
[x] 27ohm D+/D- to FT231XS
[x] DIP switch (4 switches)
[x] MAX11123 ADC SPI
[x] I2C for RTC