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208 lines
7.8 KiB
208 lines
7.8 KiB
# ULX3S PCB
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ULX3S = University digital Logic Learning Xtensible
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board release 3 with SDRAM, Successor of
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[ULX2S](http://github.com/emard/ulx2s).
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3D preview
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[Manual](/doc/MANUAL.md).
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This is a small (94x51 mm) standalone FPGA board
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for education, research and general purpose, with a full
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featured selection of chips which I all wanted on
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a low-cost PCB, but haven't found on the market.
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It's open source and open hardware because if it is
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good for our development on
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[f32c](http://github.com/f32c/f32c) SOC,
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it should be also good to other projects.
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ULX3S will carry all digital logic on our research, education and
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makerspace projects in next 5 years.
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ULX3S is standalone embeddable gadget with onboard display, buttons,
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storage, WiFi and compatible connectors.
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ULX3S can do things no other board can.
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ULX3S can self-reflash with a bitstream sent
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remotely from web interface over WiFi or from SD
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card browsed by onboard OLED display and buttons.
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ULX3S can completely power down and wakeup from
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battery backed RTC.
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ULX3S has rich range of chips and connectivity
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required for many other open source projects:
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SDRAM, USB, PS/2, SDCARD, HDMI, FLASH, RTC, I2C, OLED, AUDIO, ADC,
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onboard FM/ASK antenna 88-433.92 MHz and 56 GPIO pins which
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are all routed as differential pairs and have pinout that
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is PMOD compatible.
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ULX3S is sufficiently equipped to emulate
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[Amiga](https://github.com/emard/Minimig_ECS) retro computer and
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run its games, but can do much more.
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[Schematics](/doc/schematics.pdf) and PCB are done in open source KiCAD PCB editor:
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kicad ulx3s.pro
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[PCB v1.7](/pic/ulx3st-real.jpg) is produced.
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Important board features are tested and work like
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USB-JTAG, SDRAM, SDCARD, HDMI, FLASH, RTC, I2C, OLED, AUDIO, ADC, 433.92MHz
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US2 can be used to plug USB-PS/2 combo keyboard but US2 feature as USB
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host/device is not tested.
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There are known issues, luckily most can be fixed by
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[Upgrading PCB v1.7](/doc/pcb-v1.7-upgrade.md).
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# Features
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FPGA: Lattice ECP5 LFE5U-45F-6BG381C
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USB: FTDI FT231XS (300kbit JTAG and 3Mbit USB-serial)
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GPIO: 56 pins (28 differential pairs), PMOD-friendly
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RAM: 32MB SDRAM MT48LC16M16
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Flash: 4MB SPI Flash IS25LP032D for FPGA config
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Storage: Micro-SD slot
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LEDs: 11 (8 blink-LEDs, 2 USB LEDs, 1 WiFi LED)
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Buttons: 7 (4 direction, 2 fire, 1 power button)
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Audio: 3.5 mm jack with 4 contacts (analog stereo + digital audio or composite video)
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Video: GPDI connector with 3.3V-5V I2C bidirectional level shifter
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Display: placeholder for 0.96" SPI COLOR OLED
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WiFi+bluetooth: placeholder for ESP-32 (Standalone JTAG web interface over WiFi)
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ADC: 8 channels, 8 bit, 1 MSa/s MAX11123
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Power: 3 Switching voltage regulators: 1.1V, 2.5V, 3.3V
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Clock: 25 MHz onboard, external differential clock input
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Low power sleep: RTC clock wakeup, power button, 32768 Hz quartz and battery
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GPDI is General Purpose Differential Interface,
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Electrically LVDS, mostly TMDS tolerant
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female receptacle more-or-less compatible
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with digital monitors/TVs
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# Todo
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Test the prototype.
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[x] Silkscreen Double outline for BGA chip
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[x] Silkscreen do not write over the solder pads
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[x] Silkscreen JTAG signal names on 6-pin 2.54 mm header
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[x] Silkscreen remove OLED outline
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[x] Solder stop mask must go inbetween all SMD chip pads
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[x] External differential clock input at J1_33 +/-
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[x] physically sprinkle VCC blocator capacitors under BGA
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[ ] Values on silkscreen
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[x] Dedicated antenna pin
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[x] onboard 433 antenna
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[x] 433 remove GND and silkscreen test point
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[x] Resistors for LEDs
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[x] Move USB LEDs from bottom to top side
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[x] Improve SDRAM routing - use VIAs for closest pins
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[x] Increase thickness of power lines (5V, 3.3V, 2.5V)
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[x] Compile a f32c bitstream using the schematics
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[x] Compile differential GPDI output
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[x] Connect more lines from ESP-32 to FPGA
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[x] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[x] FPGA USB add 27 ohm + 3.6 V zener
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[x] Symmetrically place USB connectors left-right
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[x] External JTAG header
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[x] Move JTAG 2 mm left
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[x] Move WiFi Disable jumper closer to the BTN1 (angled header)
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[x] Sprinkle 2.2uF capacitors on power lines
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[x] Spice simulation of power-up/shutdown network
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[x] 27ohm D+/D- to FT231XS
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[x] DIP switch (4 switches)
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[x] MAX11123 ADC SPI
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[x] I2C for RTC
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[x] main usb connector on top side
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[x] space screw to other parts
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[x] move battery away from screw hole
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[x] top layer GND fill
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[x] R25 move away from oled screw hole
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[x] DIP switch to the right near RAM
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[x] Move HDMI a bit closer to OLED
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[x] 32768Hz oscillator footprint
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[x] SD card footprint SCHD3A0100
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[x] center the SD footprint for T&R
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[x] SD connect GND (thin pins)
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[x] move USB 0.5-1mm more out
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[x] DIP SW footprint correct
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[x] AUDIO jack footprint fits
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[x] AUDIO jack pin 4 (ring2) connected to 4-bit DAC
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[x] BTN footprint too small
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[x] SMPS jumpers default OFF for prototype testing
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[x] FPGA DONE to ESP-32
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[x] Diodes manual soldering
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[x] R56: FT231X rev A,B,C TXDEN to GND
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workaround from TN140_FT231X Errata
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[x] PCB for LFE5UM ready (some GND will change to
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VCC for Serdes power supply, see LFE5U->LFE5UM
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migration docs)
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[x] Check GND/VCC for 45 and 85 packages,
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for example pin T11 is NC on 25U, GND on 85U and VCC ond 85UM
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[x] Reconnect WIFI_OFF so that jumper has priority
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[x] 25MHz oscillator: needs clearance from LEDs, move under USB1
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[x] connect SHUTDOWN to FPGA
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[ ] ESP-32: GPIO12 at boot selects internal flash voltage,
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it is connected to J1_27+ and wrong pullup/pulldown at boot
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will prevent ESP32 from booting
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[x] ESP-32: won't boot when SD connected. Don't solder it at PCB v1.7
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It is routed differently in newer release
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Arduino->Examples->ESP32->SD_MMC_Test
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https://github.com/espressif/esp-idf/blob/master/examples/storage/sd_card/README.md
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moved blue LED from GPIO2 to GPIO5
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[x] I2C resistors increased 470->2.2k
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[x] GPDI AC-coupling 100nF to each differential line.
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[x] reliable shutdown (D11=RED LED, R4=4.7k)
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[x] SDRAM raster back to 0.8 mm
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[x] connect SPI Flash Quad Mode (QSPI)
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[x] allow powering the board without powering FTDI chip
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[ ] reverse D9 at US2 to draw power from usb instead of provide it
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[x] micro USB extended pads for Handsoldering (already were extended)
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[x] move 25MHz oscillator away from USB connector for handsoldering
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[x] schematics gpio J..+- pins renamed to gp/gn for easier readability
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[ ] route 16-channel ADC
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[x] move 8 LEDs a bit down and right
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[x] let SD_CLK go to FPGA clock capable pin: swap SD_CLK and SD_D2 pins
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[x] additional 2 differential lines for US2
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[x] additional US2 pins for pullup 1.5k
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[x] additional US2 pins for pull up-down 15k
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[x] unified US2 pullup/down: resistor-diode nework for pullup 1.5k and pulldown 15k
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[x] clear silkscreen mess with Cx under FPGA
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[x] power decoupling capacitors for ESP32 and OLED
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[x] Connect switching power supply jumpers
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[ ] every 1-2 seconds there are clicks at analog audio output
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[x] 3.6V zener diodes must be on FPGA side
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[ ] power output header: GND 1.1V 2.5V 3.3V 5V output
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[x] can esp32 second tx/rx port make serial communication with FPGA
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[x] Jumper to switch 2.5V/3.3V for left IO banks
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[x] move usb pull from gpio bank0 to gpdi bank1
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[ ] isolate each PMOD group to each io bank
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[ ] move audio L0,R2 from gpio bank7 to usb bank6
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[ ] move GP7,GP8 from gpio bank0 to gpio bank7
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[ ] route selected voltage to VCCio0/7
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[ ] route selected voltage to J1 PMOD instead of 3.3V fixed
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[ ] bank0 decoupling capacitors
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[ ] bank1 decoupling capacitors
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[ ] bank6 decoupling capacitors
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