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596 lines
24 KiB
596 lines
24 KiB
# ULX3S Manual
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# Connectors
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US1 Main micro-USB for power, program and communication.
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All onboard hardware can be programmed or reconfigured
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over US1: FPGA, FLASH, WiFi, RTC.
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US2 Auxiliary micro-USB connected directly to FPGA pins
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for experimenting with user-defined USB cores or to
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connect PS/2 keyboard or mouse using USB-OTG and
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USB-PS/2 adapters.
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Board provides power to US2.
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Board v1.7 can't be powered from US2 by default.
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Board v2.0 and higher can be powered from US2.
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If you want to power board v1.7 from US2, reverse diode
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D9 near US2 connector or short D9 with a wire.
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GPDI Plug for cable to digital monitor or TV,
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4 TMDS+- video
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1 HEAC+- ethernet and audio return
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SDA,SCL I2C (DDS EDID)
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CEC remote control
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+5V supply to enable plug-in detection
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AUDIO 3.5 mm jack with 3 channels for earphones
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and digital audio or composite video (analog TV)
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Suitable cables are 3.5mm to 3-RCA (cinch)
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Red-White-Yellow for iPhone/iBook/NOKIA.
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Sony cables are the most popular and look identical
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but are not suitable, they have GND at Ring2!
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Tip: Left analog audio
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Ring1: Right analog audio
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Ring2: Digital audio SPDIF
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Sleeve: GND
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OLED 7-pin 2.54 mm header OLED1 for SSD1331 SPI color OLED
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pinout: CS DC RES SDA SCL VCC GND
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JTAG 6-pin 2.54 mm header J4 for external JTAG programmer
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pinout: 3V3 GND
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TCK TDI
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TDO TMS
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GPIO 40-pin 2.54 mm double-row connectors J1 and J2 for GPIO
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at 3.3V logical level with 56 pins from which are:
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J1 GP,GN 0-7 are single-ended pins.
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J1 GP,GN 8-13 are differential bidirectional pairs.
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J2 GP,GN 14-21 are differential bidirectional pairs.
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J2 GP,GN 22-27 are single-ended pins.
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Differential pairs can be used also as single-ended pins.
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J1 GP,GN 12 is differential primary clock capable.
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J1 GP,GN 0,1 are single-ended primary clock capable.
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J1 GP 13 and J2 GN 17 are general routing (non-primary)
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clock capable.
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J1 pins GP,GN 9-13 are shared with ESP32 WiFi on PCB v1.7.
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J1 pins GP,GN 11-13 are shared with ESP32 WiFi on PCB >v2.0.
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J2 pins GP,GN 14-17 are shared with ADC.
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4 PMOD connectors can be made out of it
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(GND and 3.3V power are on the right place)
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J1-J2 distance is suitable to be plugged into triple
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protoboard using a single row of J1/J2.
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J2 has also 5V IN/OUT (be careful, GPIO pins are not
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5V tolerant).
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SD Micro SD card, all signal pins are routed to FPGA and
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shared with ESP-32
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ESP32 Placeholder to solder ESP-32 WROOM module.
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ESP-32 can provide standalone web interface for uploading
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bitstream into FPGA and its config FLASH.
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# Constraints (board pinout)
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For [PCB v1.7 patched for ESP32 to work](/doc/constraints/ulx3s_v17patch.lpf)
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For [PCB v2.x.x and v3.0.x](/doc/constraints/ulx3s_v20.lpf)
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# Power
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Plug US1 into PC or USB charger and board should power up.
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Initial voltage rise at USB 5V line will trigger board powering
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up and holding the power.
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On PCB v1.7, USB-serial chip FT231X will always be powered from 5V USB.
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The board has switching voltage regulators
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which can be turned off to reduce power consumption.
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On PCB v2.0 and later, USB-serial chip FT231X will be directly
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powered only from US1. If board is powered from US2, there is diode
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preventing 5V to FT231X power pin, but FT231X will still be weakly
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back-powered from its other pins connected with rest of the board
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and it will appear as some load. For most practical cases, we
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are lucky that FT231X appears as high-z when not directly powered.
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Pin loads from unpowered FT231X may sometimes prevent
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JTAG'ing from ESP32 or external JTAG, so for more reliable JTAG
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we recommend to keep FT231X powered.
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Green LED D18 behaviour is the "Power LED". Green LED ON will keep
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board powered up. By factory default, when USB-serial chip
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is enumerated by PC, Green LED will turn ON.
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Normally when board is plugged into USB charger Green LED may shortly
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blink and stay OFF, but board will keep being powered.
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Board PCB v1.7 must be hardware patched to be able to reliably
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enter shutdown mode. (It will keep waking up).
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Onboard 3V lithium battery CR1225 is only to keep RTC clock running
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and hold its configuration for a year or so. 3V battery is too
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weak to power up complete ULX3S board.
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A regulated clean and stable power supply is required,
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like USB port on PC or USB charger. 5V/0.5A should be enough for fully
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loaded and constantly active FPGA, SDRAM, LEDS, AUDIO, SD,
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ESP32 WiFi and OLED. Maximum tolerant USB voltage is 6V. Exceeding
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this limit will instantly damage the board!
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If other devices are connected and powered from ULX3S J1/J2 GPIO/PMOD
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connectors then more than 0.5A may be required - board can draw 2-3A
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when externally loaded.
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On J2 connector there are 2 pins for 5V external power input
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and output. They are located on top right, near pin labeled 27
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and US2 connector. On PCB v2.0 and later boards, both J2 5V pins are
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connected to US2 5V but there are onboard jumpers which can be
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carefully cut and schottky diodes soldered on their pads to route the
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5V power in and/or out of the board.
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Powering only from 3.3V is not possible because switching regulators
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need 5V to generate 2.5V and 1.1V.
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Switching regulators use ferrite core inductors L1,L2,L3 which can saturate
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at magnetic fields above 0.3T. Never approach neodymium magnets
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near powered board.
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# Low Power Mode
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RTC without battery will keep waking up the board as factory default.
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3V battery CR1225 and configured RTC chip is required for the board to
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enter shutdown mode. There are several ways to wake up the board:
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1) Press BTN0
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2) Re-plug US1 micro-USB cable
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3) RTC ALARM (using MCP7940N or PCF8523 arduino example)
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4) Turn on Green LED D18 (using ftx_prog or libftdi)
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Just a short pulse at RTC (ALARM INT1 shorly pull down) or
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Green LED shortly going HIGH is enough to wake up the board.
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There is SHUTDOWN pin where FPGA can turn OFF the board.
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This pin is not correctly routed on PCB v1.7 and needs
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hardware upgrade to make it work.
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To accept SHUTDOWN D18 (green LED on top side near SD card)
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must be OFF and D11 found on back side of the board near J1 pin 22.
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D18 is controlled by USB-serial chip and when lit indicates that
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USB-serial chip holds board constantly powered up.
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D11 is controlled by RTC chip and when dimly lit (visible in the dark),
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it indicates that RTC chip has ALARM INT1 pin set as inactive (high-Z, open drain).
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Due to its primary function as voltage drop in analog circuit, D11 never gets fully
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lit like other LEDs.
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RTC must have 3V battery and registers set for current time, alarm
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time and alarm logic to trigger RTC ALARM in the future. Then
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board is ready to accept SHUTDOWN signal, which is indicated when LED D11
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is very dimly lit, visible in the dark.
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While D11 is dimly lit, and D18 is OFF, board can be powered down by
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setting SHUTDOWN signal to 1 from FPGA logic or by
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connecting 1k resistor between SHUTDOWN pin of R13 and 3.3V, carefully and
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only for a moment. When RTC ALARM is triggered, RTC ALARM INT1 open-drain
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pull down will become active and board should turn ON.
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When D11 is OFF, or D18 is ON, it is indicating that board can't enter SHUTDOWN,
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probably RTC ALARM flag has to be cleared or other RTC registers configured.
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To get D18 OFF, either power board from US2 connector, power it from US1
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with charger which doesn't do USB enumeration or power it from PC at US1
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but reconfigure USB chip to turn D18 OFF:
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ftx_prog --cbus 3 DRIVE_0
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# Programming options
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To program ULX3S bitstream, there are many programming options:
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[ujprog source from GIT](https://github.com/f32c/tools)
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or [ujprog binary from EMARD](https://github.com/emard/ulx3s-bin/tree/master/usb-jtag)
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or [ujprog binary from FER](http://www.nxlab.fer.hr/dl)
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EMARD's fork of Xark's [FleaFPGA-JTAG source](https://github.com/emard/FleaFPGA-JTAG)
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or [FleaFPGA-JTAG binary](https://github.com/emard/ulx3s-bin/tree/master/usb-jtag)
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[OpenOCD soruce](https://sourceforge.net/p/openocd/code/ci/master/tree)
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or [OpenOCD binaries 2019 or later](https://github.com/gnu-mcu-eclipse/openocd/releases)
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(ft232r interface configuredd for ULX3S FT231X pinout)
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Onboard ESP32 WiFi web interface
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External USB-JTAG programmer connected to JTAG header.
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Most external JTAGs should work with OpenOCD.
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FT2232 or FT4232 JTAGs are recommended as they are
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fast, compatible and work with Lattice Diamond native programmer.
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Get Lattice original FT2232 JTAG cable or some generic FT2232 JTAG like
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[FT2232 breakout board from DangerousPrototypes](http://dangerousprototypes.com/docs/FT2232_breakout_board).
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# Programming over USB port "US1"
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Factory default (empty) onboard FT231X has to be initialized in order
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to be autodetected by "ujprog" or "FleaFPGA-JTAG" use ftx_prog.
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This needs to be done only once and board will remember it
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after power down. Settings enable max USB power consumption of 500mA
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set autodetectable product/manufacturer name of FT231X chip, serial
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number, set proper USB-serial activity LED and sets CBUS line to
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wake up board when FT231X is enumerated by host computer (PC).
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ftx_prog --max-bus-power 500
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ftx_prog --manufacturer "FER-RADIONA-EMARD"
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ftx_prog --product "ULX3S FPGA 12K v3.0.3"
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ftx_prog --new-serial-number 120001
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ftx_prog --cbus 2 TxRxLED
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ftx_prog --cbus 3 SLEEP
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Optionally you can change "45K" to "25K" or "12K" in regard with FPGA chip size.
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Re-plug the USB and it will appear as new name which can be autodetected
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with USB-serial JTAG tool.
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If running linux, some udev rule is practical in order to allow non-root users
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(in given example, members of "dialout" group) access to the USB-serial JTAG:
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# file: /etc/udev/rules.d/80-fpga-ulx3s.rules
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# this is for usb-serial tty device
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SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", \
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MODE="664", GROUP="dialout"
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# this is for ujprog libusb access
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ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015", \
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GROUP="dialout", MODE="666"
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"ujprog" tool acceps BIT or SVF files for uploading to the FPGA SRAM.
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Upload to onboard FLASH can't be yet done by "ujprog"
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ujprog bitstream-sram.bit
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ujprog bitstream-sram.svf
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"FleaFPGA-JTAG" tool accepts VME files for uploading to the FPGA SRAM or onboard
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SPI FLASH chip. SRAM VME file is simple to make, but when generating
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FLASH VME file, follow the Lattice
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TN02050 document:
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"Programming External SPI Flash through JTAG for ECP5/ECP5-5G"
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section:
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"6. Programming the SPI Flash with bitstream file using Diamond Programmer"
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and select FLASH chip type:
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Family: SPI Serial Flash
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Vendor: Micron
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Device: SPI-M25F32
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Package. 8-pin VDFPN8
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Verify: No
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When it creates VME file, pass it to FleaFPGA-JTAG argument.
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Disabled "verify" will make flashing fast, but if enabled, expect to wait
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5-15 minutes. You don't need verify because bitstream always checks
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its own CRC and it will just not load if FLASHed with errors.
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FleaFPGA-JTAG bitstream-flash.vme
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"OpenOCD" tool accepts SVF files and can upload to SRAM or onboard FLASH.
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For details see their ft232r driver documentation. In short, this
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config file should help to get started, modified to set actual
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CHIP_ID and bitstream.svf:
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file "ft231x.ocd"
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# file: ft231x.ocd
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interface ft232r
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ft232r_vid_pid 0x0403 0x6015
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# ft232r_serial_desc 123456
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ft232r_tck_num DSR
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ft232r_tms_num DCD
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ft232r_tdi_num RI
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ft232r_tdo_num CTS
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ft232r_trst_num RTS
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ft232r_srst_num DTR
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ft232r_restore_serial 0x15
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adapter_khz 1000
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file "ecp5.ocd"
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# file: ecp5.ocd
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telnet_port 4444
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gdb_port 3333
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# JTAG TAPs
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jtag newtap lfe5 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5
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# -expected-id should match ECP5 CHIP_ID:
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# 12F: 0x21111043
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# 25F: 0x41111043
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# 45F: 0x41112043
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# 85F: 0x41113043
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init
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scan_chain
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svf -tap lfe5.tap -quiet -progress bitstream.svf
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shutdown
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commandline
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openocd --file=ft231x.ocd --file=ecp5.ocd
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# Programming over USB port "US2"
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There is possibility to program ULX3S SPI config FLASH thru
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US2 connector and
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a [fork of tinyfpga bootloader](https://github.com/tinyfpga/TinyFPGA-Bootloader) loaded
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to FPGA, either loaded from US1 temporary to FPGA SRAM or permanently
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to SPI config FLASH. Bootloader uses multiboot feature of ECP5 FPGA.
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This programming option is experimental and not recommended for
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regular use.
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ULX3S with fully functional US2 bootloader can be used to program
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FPGA config FLASH without use of USB-serial chip FT231X.
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For bootloader convenience, it is recommended to solder D28 diode
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at empty placeholder located on back side near OLED and JTAG header.
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Observe diode polarity, see how other similar diodes are soldered on ULX3S.
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Any general purpose or schottky diode in SOD-323 package will fit
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like 1N914 1N4148 BAT54W etc. This diode will convert BTN0 function
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to unconditionally switch to next multiboot image by pulling down
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FPGA PROGRAMN pin.
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USB bootloader is in hacky state of development, you need hi quality
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USB cable, a compatible PC and selected USB port and too much luck (try
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all). I think bootloader's USB bus error recovery handling is wrong
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but sometimes it just works.
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US2 port should enumerate as some vendor specific USB-HID USB device
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and "tinyfpgasp" application can be used to write or read arbitrary
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image to FPGA SPI config FLASH.
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User bitstream should be uploaded to byte address 0x200000 of SPI config
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FLASH at 12/25/45F (I'm not sure for 85F).
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Bootloader in multiboot mode resides in multiple copies on SPI config
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FLASH chip. "primary"
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bootloader image is at byte address 0 of SPI config FLASH, "golden"
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bootloader image is at 0x140000 address on 45F chip but its location
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varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of
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FLASH are some special FPGA lattice boot state machine commands
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(detailed meaning and format not yet known, it's like some primitive CPU
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assembly) that setups and controls multiboot function.
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Try not to overwrite any of boot related areas with something
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else otherwise US1 or JTAG recovery will be required.
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# Programming over JTAG header
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Any openocd compatible JTAG like FT2232 can be connected to JTAG header
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and it will program SRAM and FLASH at maximum speed possible.
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Even Diamond programmer can use any FT2232 module as a native programmer,
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with a little help - it will work after first bitstream is programmed
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over FT2232 with openocd. If FT2232 is equipped with EEPROM you can use
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original "FT_PROG" for windows or this linux tool to read/write the EEPROM
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and confgure it:
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apt-get install ftdi-eeprom
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man ftdi_eeprom
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Openocd accepts SVF files, everything applies the same as for VME files
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ddtcmd -oft -svfsingle -revd -if ulx3s_flash.xcf -of bitstream.svf
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Connect JTAG cable to ULX3S JTAG header with female-female color wires.
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Carefully observe the pinout. It's standard pinout to MPSSE bus A or B
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written as TCK/TDO/TDI/TMS either on the JTAG board/cable or in
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manual/schematics. The pinout also appears as comments in the
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file "ft2232.ocd" listed below.
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To be on safe side, do not to connect 3.3V line unless required by JTAG cable manual.
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3.3V line is not needed for most cables as they use their own USB supply and
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have default 3.3V TTL level. 3.3V power rail from ULX3S is 2A current
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capable and can damage the cable if accidentally connected to wrong pin.
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For FT2232 generic cable, this openocd config file can be used with above
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file "ecp5.ocd" to program "bitstream.svf":
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file "ft2232.ocd"
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# file: ft2232.ocd
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interface ftdi
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# ftdi_device_desc "Dual RS232-HS"
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ftdi_vid_pid 0x0403 0x6010
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ftdi_layout_init 0x3088 0x1f8b
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# default is port A if unspecified
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# pinout ADBUS 0-TCK 1-TDI 2-TDO 3-TMS
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#ftdi_channel 0
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# uncomment this to use port B
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# pinout BDBUS 0-TCK 1-TDI 2-TDO 3-TMS
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#ftdi_channel 1
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adapter_khz 25000
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commandline
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openocd --file=ft2232.ocd --file=ecp5.ocd
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External FT2232 JTAG cable can be used by Lattice Diamond native programmer
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on linux. Prior to use the FT2232 port A or B which is connected as JTAG,
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USB-serial kernel driver must be detached from the FT2232 port.
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To detach detach port B manually:
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ls /sys/bus/usb/drivers/ftdi_sio
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1-6.2:1.0 1-6.2:1.1 bind module uevent unbind
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echo -n "1-6.2:1.1" > /sys/bus/usb/drivers/ftdi_sio/unbind
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To detach port B automatically:
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#/bin/bash
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allow_io=`lsusb | sed -n 's/^Bus \([0-9]*\) Device \([0-9]*\): ID 0403:6010 .*/\1\/\2/p'`
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unbind_tty=`ls /sys/bus/usb/drivers/ftdi_sio/ | sed -n 's/\(.*\:1\.1\).*/\1/p'`
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sudo chmod a+rw \/dev\/bus\/usb\/$allow_io
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sudo sh -c "echo $unbind_tty > /sys/bus/usb/drivers/ftdi_sio/unbind"
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When USB-serial driver is detached from port A or B, Lattice Diamond programmer
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can use this port as native JTAG programmer.
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For JTAG sharing with ESP32 port B should be set to high impedance
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and the experimentally found solution is to set this port to FIFO or OPTO
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using "ftdi_eeprom" tool
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apt-get install ftdi_eeprom
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make "ftdi_eeprom.conf" config file, set manufacturer/product strings
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to your liking but important line for high impedance for port B is
|
|
to set it as FIFO or OPTO:
|
|
|
|
chb_type=FIFO
|
|
|
|
write config to eeprom:
|
|
|
|
ftdi_eeprom --flash-eeprom ftdi_eeprom.conf
|
|
|
|
re-plug USB to reload new eeprom content.
|
|
|
|
# Programming over WiFi
|
|
|
|
ESP-32 provides standalone JTAG SVF player over web HTTP and TCP interface for
|
|
programming and flashing in convenient and OS independent way. Web interface
|
|
requires no client software installed but web browser. It is much faster than
|
|
FT231X but still not as fast as FT2232. It accepts SVF files but you need to limit
|
|
SVF command size to max 8 kilobits "-maxdata 8", effectively it will split
|
|
upload into many shorter SVF commands because ESP-32 doesn't have enough
|
|
memory to buffer entire bitstream delivered in a long single SVF command.
|
|
|
|
ddtcmd -oft -svfsingle -revd -maxdata 8 -if ulx3s_flash.xcf -of bitstream.svf
|
|
|
|
To start using ESP-32 first you need to compile
|
|
[ULX3S passthru](https://github.com/emard/ulx3s-passthru)
|
|
and upload it using FleaFPGA-JTAG or external JTAG programmer.
|
|
"Passthru" bitstream configures FPGA to route lines from USB-serial to ESP-32.
|
|
|
|
Then you need to install Arduino and its ESP-32 support, and
|
|
install Emard's library [LibXSVF-ESP](https://github.com/emard/LibXSVF-ESP),
|
|
required library dependencies and
|
|
[ESP-32 SPIFFS uploader](https://github.com/me-no-dev/arduino-esp32fs-plugin/releases/tag/v0.1)
|
|
Version "ESP32FS-v0.1.zip" worked for me.
|
|
|
|
In Arduino boards manager select this ESP-32 board:
|
|
|
|
DOIT ESP32 DEVKIT V1
|
|
|
|
Select "Examples->LibXSVF->websvf" and optionally change
|
|
its default ssid/password. Compile and upload the code by
|
|
clicking "Sketch->Upload", check reports on lower terminal
|
|
window, successfull upload will finish with this:
|
|
|
|
Hash of data verified.
|
|
Leaving...
|
|
Hard resetting...
|
|
|
|
Then upload the web page content to ESP-32 FLASH filesystem,
|
|
at websvf window click "Tools->ESP32 Sketch Data Upload".
|
|
successful upload will finish with same as above.
|
|
|
|
ESP32 will try to connect to your local WiFi as client with
|
|
default ssid=websvf password=12345678
|
|
Insert SD card with file "ulx3s-wifi.conf" in SD root directory:
|
|
|
|
{
|
|
"host_name": "ulx3s",
|
|
"ssid": "ulx3s",
|
|
"password": "testpass",
|
|
"http_username": "user",
|
|
"http_password": "pass"
|
|
}
|
|
|
|
By editing this file you can set
|
|
ssid and password for connection
|
|
to your local WiFi access point.
|
|
|
|
If client connection is unsuccessful ESP-32 it will become
|
|
access point with the same ssid and password, but so far many people
|
|
reported unsuccessful connection attempts from PC to ESP-32 in AP mode.
|
|
If you want to try, AP mode ESP-32 web address is "http://192.168.4.1"
|
|
and internet should not to work in this case :).
|
|
|
|
If ESP-32 connected as a client, IP address will vary depending
|
|
on local network. Discover it by using WiFi access
|
|
point web interface, ARP, NMAP, or by sniffing it.
|
|
On the ESP-32 page something like this will appear:
|
|
|
|
Select SVF File or use minimal or svfupload.py
|
|
[File] File not selected
|
|
[Upload]
|
|
[0% ]
|
|
|
|
Navigate file selector to bitstream.svf file, it will show
|
|
its size in KB. Then click "Upload", progress bar will run
|
|
from 0% to 100% in few seconds (if it's SRAM upload) and
|
|
bitstream will be started. FLASH can also be written from
|
|
web iterface it takes 2-3 minutes. Also on the web interface
|
|
there's available for download a small python commandline
|
|
upload tool.
|
|
|
|
Note that FPGA can enable or disable ESP-32 module. If ESP-32
|
|
is disabled by newly uploaded bistream, some alert window will
|
|
pop-up after otherwise successful upload because ESP-32 cannot
|
|
close HTTP session properly.
|
|
To make it go smooth, in the bitstream make FPGA pin "wifi_en"
|
|
as input (HIGH-impedance, pull up).
|
|
|
|
Technically, ESP-32 can be loaded with such a code that
|
|
permanently holds JTAG lines while FPGA can at the same time
|
|
have in FLASH a bitstream that permanenly enables ESP-32.
|
|
Such combination will preventing JTAG from working so
|
|
ULX3S board may become "Bricked". There is jumper J3 to disable
|
|
ESP-32, its left of SD card slot. Note boards PCB v1.7 need
|
|
upgrade for this jumper to work correctly.
|
|
|
|
# Programming ESP32
|
|
|
|
ESP32 WiFi module soldered on ULX3S is usually shipped
|
|
to end-users with WiFi Web-JTAG application loaded in ESP32.
|
|
User can overwrite ESP32 with any other sketch like "blink"
|
|
and then ESP32 Web-JTAG interface will temporarily disappear.
|
|
|
|
Web-JTAG ESP32 application can be restored back to factory
|
|
default state using binaries and linux scripts
|
|
from [ulx3s-bin](https://github.com/emard/ulx3s-bin) or
|
|
by recompiling from [LibXSVF-ESP Source](https://github.com/emard/LibXSVF-ESP).
|
|
|
|
Load "passthru" bitstream to FPGA config flash, install
|
|
Arduino and its ESP32 support. In "tools" pull down menu, under ESP32
|
|
select board "WEMOS LOLIN32" and normally program ULX3S onboard ESP32
|
|
from Arduino by clicking right arrow round button (->) to upload sketch.
|
|
Examples->Digital->Blink_without_delay any you should see blue LED D22
|
|
blinking.
|
|
|
|
This automagically works because "passthru" bitstream will
|
|
redirect USB-serial ESP32 programming traffic from PC thru FPGA to ESP32.
|
|
|
|
|
|
There might be strange issues on getting this to work on windows.
|
|
On linux usually only USB-serial port access permission is required.
|
|
|
|
# Board Versions
|
|
|
|
This project is open source, freely downloadable so there can be
|
|
as many versions as here are git commits.
|
|
|
|
v3.0.3 is currently the only version which is officially being sold
|
|
at [skriptarnica](http://skriptarnica.hr/vijest.aspx?newsID=1466).
|
|
Other versions are either prototypes or independently produced.
|
|
|
|
Up to our knowledge those versions are currently circulating around.
|
|
All listed versions should work if all parts (notably BGA) are properly
|
|
soldered.
|
|
|
|
PCB assembly quantity constraints
|
|
version facility produced date compatibility note
|
|
------- ------------ -------- ---------- ------------- --------
|
|
v1.7 PCBWay 8 dec 2017 v17patch prototype
|
|
v1.7 lemilica.com 1 jan 2018 v17patch handwork
|
|
v1.8 PCBWay 10 may 2018 v18 prototype
|
|
v2.0.3 q3k 1 aug 2018 v20 handwork
|
|
v2.1.2 INEM-KONČAR 35 sep 2018 v20 prototype
|
|
v3.0.3 INEM-KONČAR 220 oct 2018 v20 for sale
|
|
v2.0.5 Marvin 1 nov 2018 v20 handwork
|
|
v3.0.3 INEM-KONČAR 35 jan 2019 v20 for sale
|