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@ -60,9 +60,12 @@
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*
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*
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* Note that this design currently has several limitations:
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* Note that this design currently has several limitations:
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* - Minimum target clock speed of 500KHz due to hardware SPI used
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* - Minimum target clock speed of 500KHz due to hardware SPI used
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* - No VTARGET detection and notification
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* - No reversed/shorted target connector detection and notification
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* - No reversed/shorted target connector detection and notification
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*
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*
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* On AVR models with an ADC converter, ACC should be tied to 5V (e.g. VBUS) and the VTARGET_ADC_CHANNEL token should be
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* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models
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* without an ADC converter, VTARGET will report at a fixed 5V level.
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*
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* \section SSec_Options Project Options
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* \section SSec_Options Project Options
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*
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*
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* The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.
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* The following defines can be found in this demo, which can control the demo behaviour when defined, or changed in value.
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@ -88,5 +91,10 @@
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>Mask for the programmer's target RESET line on the chosen port.</td>
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* <td>Mask for the programmer's target RESET line on the chosen port.</td>
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* </tr>
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* </tr>
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* <tr>
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* <td>VTARGET_ADC_CHANNEL</td>
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* <td>Makefile CDEFS</td>
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* <td>ADC channel number (on supported AVRs) to use for VTARGET level detection.</td>
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* </tr>
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* </table>
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* </table>
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*/
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*/
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