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@ -9,22 +9,25 @@
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#include "i2c_slave.h"
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#include "i2c_slave.h"
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void i2c_init(uint8_t address){
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volatile uint8_t i2c_slave_reg[I2C_SLAVE_REG_COUNT];
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static volatile uint8_t buffer_address;
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static volatile bool slave_has_register_set = false;
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void i2c_slave_init(uint8_t address){
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// load address into TWI address register
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// load address into TWI address register
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TWAR = (address << 1);
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TWAR = (address << 1);
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// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
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// set the TWCR to enable address matching and enable TWI, clear TWINT, enable TWI interrupt
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TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN);
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TWCR = (1 << TWIE) | (1 << TWEA) | (1 << TWINT) | (1 << TWEN);
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}
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}
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void i2c_stop(void){
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void i2c_slave_stop(void){
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// clear acknowledge and enable bits
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// clear acknowledge and enable bits
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TWCR &= ~((1 << TWEA) | (1 << TWEN));
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TWCR &= ~((1 << TWEA) | (1 << TWEN));
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}
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}
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ISR(TWI_vect){
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ISR(TWI_vect){
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uint8_t ack = 1;
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uint8_t ack = 1;
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// temporary stores the received data
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//uint8_t data;
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switch(TW_STATUS){
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switch(TW_STATUS){
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case TW_SR_SLA_ACK:
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case TW_SR_SLA_ACK:
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@ -38,13 +41,13 @@ ISR(TWI_vect){
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if(!slave_has_register_set){
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if(!slave_has_register_set){
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buffer_address = TWDR;
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buffer_address = TWDR;
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if (buffer_address >= RX_BUFFER_SIZE){ // address out of bounds dont ack
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if (buffer_address >= I2C_SLAVE_REG_COUNT) { // address out of bounds dont ack
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ack = 0;
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ack = 0;
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buffer_address = 0;
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buffer_address = 0;
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}
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}
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slave_has_register_set = true; // address has been receaved now fill in buffer
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slave_has_register_set = true; // address has been receaved now fill in buffer
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} else {
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} else {
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rxbuffer[buffer_address] = TWDR;
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i2c_slave_reg[buffer_address] = TWDR;
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buffer_address++;
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buffer_address++;
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}
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}
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break;
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break;
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@ -52,7 +55,7 @@ ISR(TWI_vect){
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case TW_ST_SLA_ACK:
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case TW_ST_SLA_ACK:
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case TW_ST_DATA_ACK:
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case TW_ST_DATA_ACK:
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// This device is a slave transmitter and master has requested data
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// This device is a slave transmitter and master has requested data
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TWDR = txbuffer[buffer_address];
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TWDR = i2c_slave_reg[buffer_address];
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buffer_address++;
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buffer_address++;
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break;
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break;
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@ -63,6 +66,6 @@ ISR(TWI_vect){
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break;
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break;
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}
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}
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// Reset i2c state mahcine to be ready for next interrupt
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// Reset i2c state machine to be ready for next interrupt
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TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN);
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TWCR |= (1 << TWIE) | (1 << TWINT) | (ack << TWEA) | (1 << TWEN);
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}
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}
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