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@ -162,7 +162,7 @@ void XPROGTarget_EnableTargetPDI(void)
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/* Set up the synchronous USART for XMEGA communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 500000UL);
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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@ -203,7 +203,7 @@ void XPROGTarget_EnableTargetTPI(void)
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/* Set up the synchronous USART for TINY communications -
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8 data bits, even parity, 2 stop bits */
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UBRR1 = (F_CPU / 500000UL);
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UBRR1 = (F_CPU / XPROG_HARDWARE_SPEED);
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UCSR1B = (1 << TXEN1);
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UCSR1C = (1 << UMSEL10) | (1 << UPM11) | (1 << USBS1) | (1 << UCSZ11) | (1 << UCSZ10) | (1 << UCPOL1);
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#else
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@ -239,16 +239,18 @@ void XPROGTarget_DisableTargetPDI(void)
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/* Tristate all pins */
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DDRD &= ~((1 << 5) | (1 << 3));
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PORTD &= ~((1 << 3) | (1 << 2));
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PORTD &= ~((1 << 5) | (1 << 3) | (1 << 2));
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#else
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/* Turn off software USART management timer */
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TCCR1B = 0;
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/* Tristate all pins */
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/* Set DATA and CLOCK lines to inputs */
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BITBANG_PDIDATA_DDR &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_DDR &= ~BITBANG_PDICLOCK_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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/* Tristate DATA and CLOCK lines */
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BITBANG_PDIDATA_PORT &= ~BITBANG_PDIDATA_MASK;
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BITBANG_PDICLOCK_PORT &= ~BITBANG_PDICLOCK_MASK;
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#endif
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}
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