Rgb matrix fixes, I2C library can now retry if it has failed (#2943)
* Added Modular keyboards L,R and NUM Created code modules for the 3 modules of the modular keyboard. Original idea by MechboardsUK. Uses i2c implementation similar to lets split * Remove modular from master This is to fix incorrect branching * General fixes for RGB_matrix - Complited speed support for all effects - Fixed raindrop effects to initialized after toggle - Fixed raindrop effects to use all available LEDs - Fixed effect step reverse function - Moved RGB_MATRIX_SOLID_REACTIVE under correct flag * Documentation update for RGBmatrix * More doc updates * I2C library can now retry if it has failed - Replaced the original TWIlib by LFKeyboard's modified version - Allows for an extra argument on TWITransmitData, if blocking is set to 1 function will retry to transmit on failure. Good for noisy boards. * RGB Matrix, use alternative I2C library TWIlib seems to be hanging for me sometimes probably due to ISR routine. I have used i2c_master as a good alternative. Note: this commit is for Wilba6582 to verify before merge * Update rgb_matrix.c * RGB matrix cleanup - Remove TWIlibpull/2967/head
yiancar
7 years ago
committed by
Jack Humbert
parent
f42ec8aa86
commit
a98a91cf1b
@ -1,232 +0,0 @@
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/*
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* TWIlib.c
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*
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* Created: 6/01/2014 10:41:33 PM
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* Author: Chris Herring
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* http://www.chrisherring.net/all/tutorial-interrupt-driven-twi-interface-for-avr-part1/
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*/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include "TWIlib.h"
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#include "util/delay.h"
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void TWIInit()
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{
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TWIInfo.mode = Ready;
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TWIInfo.errorCode = 0xFF;
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TWIInfo.repStart = 0;
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// Set pre-scalers (no pre-scaling)
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TWSR = 0;
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// Set bit rate
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TWBR = ((F_CPU / TWI_FREQ) - 16) / 2;
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// Enable TWI and interrupt
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TWCR = (1 << TWIE) | (1 << TWEN);
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}
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uint8_t isTWIReady()
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{
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if ( (TWIInfo.mode == Ready) | (TWIInfo.mode == RepeatedStartSent) )
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{
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return 1;
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}
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else
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{
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return 0;
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}
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}
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uint8_t TWITransmitData(void *const TXdata, uint8_t dataLen, uint8_t repStart)
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{
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if (dataLen <= TXMAXBUFLEN)
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{
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// Wait until ready
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while (!isTWIReady()) {_delay_us(1);}
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// Set repeated start mode
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TWIInfo.repStart = repStart;
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// Copy data into the transmit buffer
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uint8_t *data = (uint8_t *)TXdata;
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for (int i = 0; i < dataLen; i++)
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{
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TWITransmitBuffer[i] = data[i];
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}
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// Copy transmit info to global variables
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TXBuffLen = dataLen;
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TXBuffIndex = 0;
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// If a repeated start has been sent, then devices are already listening for an address
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// and another start does not need to be sent.
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if (TWIInfo.mode == RepeatedStartSent)
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{
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TWIInfo.mode = Initializing;
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TWDR = TWITransmitBuffer[TXBuffIndex++]; // Load data to transmit buffer
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TWISendTransmit(); // Send the data
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}
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else // Otherwise, just send the normal start signal to begin transmission.
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{
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TWIInfo.mode = Initializing;
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TWISendStart();
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}
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}
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else
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{
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return 1; // return an error if data length is longer than buffer
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}
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return 0;
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}
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uint8_t TWIReadData(uint8_t TWIaddr, uint8_t bytesToRead, uint8_t repStart)
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{
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// Check if number of bytes to read can fit in the RXbuffer
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if (bytesToRead < RXMAXBUFLEN)
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{
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// Reset buffer index and set RXBuffLen to the number of bytes to read
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RXBuffIndex = 0;
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RXBuffLen = bytesToRead;
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// Create the one value array for the address to be transmitted
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uint8_t TXdata[1];
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// Shift the address and AND a 1 into the read write bit (set to write mode)
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TXdata[0] = (TWIaddr << 1) | 0x01;
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// Use the TWITransmitData function to initialize the transfer and address the slave
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TWITransmitData(TXdata, 1, repStart);
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}
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else
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{
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return 0;
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}
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return 1;
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}
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ISR (TWI_vect)
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{
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switch (TWI_STATUS)
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{
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// ----\/ ---- MASTER TRANSMITTER OR WRITING ADDRESS ----\/ ---- //
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case TWI_MT_SLAW_ACK: // SLA+W transmitted and ACK received
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// Set mode to Master Transmitter
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TWIInfo.mode = MasterTransmitter;
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case TWI_START_SENT: // Start condition has been transmitted
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case TWI_MT_DATA_ACK: // Data byte has been transmitted, ACK received
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if (TXBuffIndex < TXBuffLen) // If there is more data to send
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{
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TWDR = TWITransmitBuffer[TXBuffIndex++]; // Load data to transmit buffer
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TWIInfo.errorCode = TWI_NO_RELEVANT_INFO;
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TWISendTransmit(); // Send the data
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}
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// This transmission is complete however do not release bus yet
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else if (TWIInfo.repStart)
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{
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TWIInfo.errorCode = 0xFF;
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TWISendStart();
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}
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// All transmissions are complete, exit
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else
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{
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TWIInfo.mode = Ready;
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TWIInfo.errorCode = 0xFF;
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TWISendStop();
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}
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break;
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// ----\/ ---- MASTER RECEIVER ----\/ ---- //
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case TWI_MR_SLAR_ACK: // SLA+R has been transmitted, ACK has been received
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// Switch to Master Receiver mode
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TWIInfo.mode = MasterReceiver;
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// If there is more than one byte to be read, receive data byte and return an ACK
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if (RXBuffIndex < RXBuffLen-1)
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{
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TWIInfo.errorCode = TWI_NO_RELEVANT_INFO;
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TWISendACK();
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}
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// Otherwise when a data byte (the only data byte) is received, return NACK
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else
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{
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TWIInfo.errorCode = TWI_NO_RELEVANT_INFO;
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TWISendNACK();
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}
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break;
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case TWI_MR_DATA_ACK: // Data has been received, ACK has been transmitted.
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/// -- HANDLE DATA BYTE --- ///
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TWIReceiveBuffer[RXBuffIndex++] = TWDR;
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// If there is more than one byte to be read, receive data byte and return an ACK
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if (RXBuffIndex < RXBuffLen-1)
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{
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TWIInfo.errorCode = TWI_NO_RELEVANT_INFO;
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TWISendACK();
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}
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// Otherwise when a data byte (the only data byte) is received, return NACK
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else
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{
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TWIInfo.errorCode = TWI_NO_RELEVANT_INFO;
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TWISendNACK();
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}
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break;
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case TWI_MR_DATA_NACK: // Data byte has been received, NACK has been transmitted. End of transmission.
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/// -- HANDLE DATA BYTE --- ///
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TWIReceiveBuffer[RXBuffIndex++] = TWDR;
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// This transmission is complete however do not release bus yet
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if (TWIInfo.repStart)
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{
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TWIInfo.errorCode = 0xFF;
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TWISendStart();
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}
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// All transmissions are complete, exit
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else
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{
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TWIInfo.mode = Ready;
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TWIInfo.errorCode = 0xFF;
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TWISendStop();
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}
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break;
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// ----\/ ---- MT and MR common ----\/ ---- //
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case TWI_MR_SLAR_NACK: // SLA+R transmitted, NACK received
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case TWI_MT_SLAW_NACK: // SLA+W transmitted, NACK received
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case TWI_MT_DATA_NACK: // Data byte has been transmitted, NACK received
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case TWI_LOST_ARBIT: // Arbitration has been lost
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// Return error and send stop and set mode to ready
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if (TWIInfo.repStart)
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{
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TWIInfo.errorCode = TWI_STATUS;
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TWISendStart();
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}
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// All transmissions are complete, exit
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else
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{
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TWIInfo.mode = Ready;
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TWIInfo.errorCode = TWI_STATUS;
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TWISendStop();
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}
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break;
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case TWI_REP_START_SENT: // Repeated start has been transmitted
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// Set the mode but DO NOT clear TWINT as the next data is not yet ready
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TWIInfo.mode = RepeatedStartSent;
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break;
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// ----\/ ---- SLAVE RECEIVER ----\/ ---- //
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// TODO IMPLEMENT SLAVE RECEIVER FUNCTIONALITY
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// ----\/ ---- SLAVE TRANSMITTER ----\/ ---- //
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// TODO IMPLEMENT SLAVE TRANSMITTER FUNCTIONALITY
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// ----\/ ---- MISCELLANEOUS STATES ----\/ ---- //
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case TWI_NO_RELEVANT_INFO: // It is not really possible to get into this ISR on this condition
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// Rather, it is there to be manually set between operations
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break;
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case TWI_ILLEGAL_START_STOP: // Illegal START/STOP, abort and return error
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TWIInfo.errorCode = TWI_ILLEGAL_START_STOP;
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TWIInfo.mode = Ready;
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TWISendStop();
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break;
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}
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}
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@ -1,82 +0,0 @@
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/*
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* TWIlib.h
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*
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* Created: 6/01/2014 10:38:42 PM
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* Author: Chris Herring
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* http://www.chrisherring.net/all/tutorial-interrupt-driven-twi-interface-for-avr-part1/
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*/
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#ifndef TWILIB_H_
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#define TWILIB_H_
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// TWI bit rate (was 100000)
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#define TWI_FREQ 400000
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// Get TWI status
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#define TWI_STATUS (TWSR & 0xF8)
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// Transmit buffer length
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#define TXMAXBUFLEN 20
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// Receive buffer length
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#define RXMAXBUFLEN 20
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// Global transmit buffer
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uint8_t TWITransmitBuffer[TXMAXBUFLEN];
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// Global receive buffer
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volatile uint8_t TWIReceiveBuffer[RXMAXBUFLEN];
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// Buffer indexes
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volatile int TXBuffIndex; // Index of the transmit buffer. Is volatile, can change at any time.
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int RXBuffIndex; // Current index in the receive buffer
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// Buffer lengths
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int TXBuffLen; // The total length of the transmit buffer
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int RXBuffLen; // The total number of bytes to read (should be less than RXMAXBUFFLEN)
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typedef enum {
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Ready,
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Initializing,
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RepeatedStartSent,
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MasterTransmitter,
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MasterReceiver,
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SlaceTransmitter,
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SlaveReciever
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} TWIMode;
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typedef struct TWIInfoStruct{
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TWIMode mode;
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uint8_t errorCode;
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uint8_t repStart;
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}TWIInfoStruct;
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TWIInfoStruct TWIInfo;
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// TWI Status Codes
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#define TWI_START_SENT 0x08 // Start sent
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#define TWI_REP_START_SENT 0x10 // Repeated Start sent
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// Master Transmitter Mode
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#define TWI_MT_SLAW_ACK 0x18 // SLA+W sent and ACK received
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#define TWI_MT_SLAW_NACK 0x20 // SLA+W sent and NACK received
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#define TWI_MT_DATA_ACK 0x28 // DATA sent and ACK received
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#define TWI_MT_DATA_NACK 0x30 // DATA sent and NACK received
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// Master Receiver Mode
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#define TWI_MR_SLAR_ACK 0x40 // SLA+R sent, ACK received
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#define TWI_MR_SLAR_NACK 0x48 // SLA+R sent, NACK received
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#define TWI_MR_DATA_ACK 0x50 // Data received, ACK returned
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#define TWI_MR_DATA_NACK 0x58 // Data received, NACK returned
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// Miscellaneous States
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#define TWI_LOST_ARBIT 0x38 // Arbitration has been lost
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#define TWI_NO_RELEVANT_INFO 0xF8 // No relevant information available
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#define TWI_ILLEGAL_START_STOP 0x00 // Illegal START or STOP condition has been detected
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#define TWI_SUCCESS 0xFF // Successful transfer, this state is impossible from TWSR as bit2 is 0 and read only
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#define TWISendStart() (TWCR = (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)|(1<<TWIE)) // Send the START signal, enable interrupts and TWI, clear TWINT flag to resume transfer.
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#define TWISendStop() (TWCR = (1<<TWINT)|(1<<TWSTO)|(1<<TWEN)|(1<<TWIE)) // Send the STOP signal, enable interrupts and TWI, clear TWINT flag.
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#define TWISendTransmit() (TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWIE)) // Used to resume a transfer, clear TWINT and ensure that TWI and interrupts are enabled.
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#define TWISendACK() (TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWIE)|(1<<TWEA)) // FOR MR mode. Resume a transfer, ensure that TWI and interrupts are enabled and respond with an ACK if the device is addressed as a slave or after it receives a byte.
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#define TWISendNACK() (TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWIE)) // FOR MR mode. Resume a transfer, ensure that TWI and interrupts are enabled but DO NOT respond with an ACK if the device is addressed as a slave or after it receives a byte.
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// Function declarations
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uint8_t TWITransmitData(void *const TXdata, uint8_t dataLen, uint8_t repStart);
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void TWIInit(void);
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uint8_t TWIReadData(uint8_t TWIaddr, uint8_t bytesToRead, uint8_t repStart);
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uint8_t isTWIReady(void);
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#endif // TWICOMMS_H_
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@ -0,0 +1,149 @@
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/* Library made by: g4lvanix
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* Github repository: https://github.com/g4lvanix/I2C-master-lib
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*/
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#include <avr/io.h>
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#include <util/twi.h>
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#include "i2c_master.h"
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#define F_SCL 400000UL // SCL frequency
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#define Prescaler 1
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#define TWBR_val ((((F_CPU / F_SCL) / Prescaler) - 16 ) / 2)
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void i2c_init(void)
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{
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TWBR = (uint8_t)TWBR_val;
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}
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uint8_t i2c_start(uint8_t address)
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{
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// reset TWI control register
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TWCR = 0;
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// transmit START condition
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TWCR = (1<<TWINT) | (1<<TWSTA) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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// check if the start condition was successfully transmitted
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if((TWSR & 0xF8) != TW_START){ return 1; }
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// load slave address into data register
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TWDR = address;
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// start transmission of address
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TWCR = (1<<TWINT) | (1<<TWEN);
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// wait for end of transmission
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while( !(TWCR & (1<<TWINT)) );
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// check if the device has acknowledged the READ / WRITE mode
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uint8_t twst = TW_STATUS & 0xF8;
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if ( (twst != TW_MT_SLA_ACK) && (twst != TW_MR_SLA_ACK) ) return 1;
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return 0;
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}
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uint8_t i2c_write(uint8_t data)
|
||||||
|
{
|
||||||
|
// load data into data register
|
||||||
|
TWDR = data;
|
||||||
|
// start transmission of data
|
||||||
|
TWCR = (1<<TWINT) | (1<<TWEN);
|
||||||
|
// wait for end of transmission
|
||||||
|
while( !(TWCR & (1<<TWINT)) );
|
||||||
|
|
||||||
|
if( (TWSR & 0xF8) != TW_MT_DATA_ACK ){ return 1; }
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_read_ack(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
// start TWI module and acknowledge data after reception
|
||||||
|
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWEA);
|
||||||
|
// wait for end of transmission
|
||||||
|
while( !(TWCR & (1<<TWINT)) );
|
||||||
|
// return received data from TWDR
|
||||||
|
return TWDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_read_nack(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
// start receiving without acknowledging reception
|
||||||
|
TWCR = (1<<TWINT) | (1<<TWEN);
|
||||||
|
// wait for end of transmission
|
||||||
|
while( !(TWCR & (1<<TWINT)) );
|
||||||
|
// return received data from TWDR
|
||||||
|
return TWDR;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_transmit(uint8_t address, uint8_t* data, uint16_t length)
|
||||||
|
{
|
||||||
|
if (i2c_start(address | I2C_WRITE)) return 1;
|
||||||
|
|
||||||
|
for (uint16_t i = 0; i < length; i++)
|
||||||
|
{
|
||||||
|
if (i2c_write(data[i])) return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_stop();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length)
|
||||||
|
{
|
||||||
|
if (i2c_start(address | I2C_READ)) return 1;
|
||||||
|
|
||||||
|
for (uint16_t i = 0; i < (length-1); i++)
|
||||||
|
{
|
||||||
|
data[i] = i2c_read_ack();
|
||||||
|
}
|
||||||
|
data[(length-1)] = i2c_read_nack();
|
||||||
|
|
||||||
|
i2c_stop();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length)
|
||||||
|
{
|
||||||
|
if (i2c_start(devaddr | 0x00)) return 1;
|
||||||
|
|
||||||
|
i2c_write(regaddr);
|
||||||
|
|
||||||
|
for (uint16_t i = 0; i < length; i++)
|
||||||
|
{
|
||||||
|
if (i2c_write(data[i])) return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_stop();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length)
|
||||||
|
{
|
||||||
|
if (i2c_start(devaddr)) return 1;
|
||||||
|
|
||||||
|
i2c_write(regaddr);
|
||||||
|
|
||||||
|
if (i2c_start(devaddr | 0x01)) return 1;
|
||||||
|
|
||||||
|
for (uint16_t i = 0; i < (length-1); i++)
|
||||||
|
{
|
||||||
|
data[i] = i2c_read_ack();
|
||||||
|
}
|
||||||
|
data[(length-1)] = i2c_read_nack();
|
||||||
|
|
||||||
|
i2c_stop();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void i2c_stop(void)
|
||||||
|
{
|
||||||
|
// transmit STOP condition
|
||||||
|
TWCR = (1<<TWINT) | (1<<TWEN) | (1<<TWSTO);
|
||||||
|
}
|
||||||
@ -0,0 +1,22 @@
|
|||||||
|
/* Library made by: g4lvanix
|
||||||
|
* Github repository: https://github.com/g4lvanix/I2C-master-lib
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef I2C_MASTER_H
|
||||||
|
#define I2C_MASTER_H
|
||||||
|
|
||||||
|
#define I2C_READ 0x01
|
||||||
|
#define I2C_WRITE 0x00
|
||||||
|
|
||||||
|
void i2c_init(void);
|
||||||
|
uint8_t i2c_start(uint8_t address);
|
||||||
|
uint8_t i2c_write(uint8_t data);
|
||||||
|
uint8_t i2c_read_ack(void);
|
||||||
|
uint8_t i2c_read_nack(void);
|
||||||
|
uint8_t i2c_transmit(uint8_t address, uint8_t* data, uint16_t length);
|
||||||
|
uint8_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length);
|
||||||
|
uint8_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length);
|
||||||
|
uint8_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length);
|
||||||
|
void i2c_stop(void);
|
||||||
|
|
||||||
|
#endif // I2C_MASTER_H
|
||||||
Loading…
Reference in new issue