Changed the XPLAINBridge software UART to use the regular CTC mode instead of the alternative CTC mode via the Input Capture register, to reduce user confusion.

pull/1469/head
Dean Camera 14 years ago
parent fd77bf5c94
commit b634ec50a0

@ -11,13 +11,14 @@
* - Core: * - Core:
* - None * - None
* - Library Applications: * - Library Applications:
* - None * - Added new incomplete MIDIToneGenerator project
* *
* <b>Changed:</b> * <b>Changed:</b>
* - Core: * - Core:
* - None * - None
* - Library Applications: * - Library Applications:
* - None * - Changed the XPLAINBridge software UART to use the regular CTC mode instead of the alternative CTC mode
* via the Input Capture register, to reduce user confusion
* *
* <b>Fixed:</b> * <b>Fixed:</b>
* - Core: * - Core:

@ -11,7 +11,7 @@
volatile clock_time_t clock_datetime = 0; volatile clock_time_t clock_datetime = 0;
//Overflow interrupt //Overflow interrupt
ISR(TIMER1_COMPA_vect) ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{ {
clock_datetime += 1; clock_datetime += 1;
} }

@ -67,11 +67,11 @@ void SoftUART_Init(void)
SoftUART_SetBaud(9600); SoftUART_SetBaud(9600);
/* Setup reception timer compare ISR */ /* Setup reception timer compare ISR */
TIMSK1 = (1 << ICIE1); TIMSK1 = (1 << OC1E1A);
/* Setup transmission timer compare ISR and start the timer */ /* Setup transmission timer compare ISR and start the timer */
TIMSK3 = (1 << ICIE3); TIMSK3 = (1 << OC1E3A);
TCCR3B = ((1 << CS30) | (1 << WGM33) | (1 << WGM32)); TCCR3B = ((1 << CS30) | (1 << WGM32));
} }
/** ISR to detect the start of a bit being sent to the software UART. */ /** ISR to detect the start of a bit being sent to the software UART. */
@ -90,12 +90,12 @@ ISR(INT0_vect, ISR_BLOCK)
EIMSK = 0; EIMSK = 0;
/* Start the reception timer */ /* Start the reception timer */
TCCR1B = ((1 << CS10) | (1 << WGM13) | (1 << WGM12)); TCCR1B = ((1 << CS10) | (1 << WGM12));
} }
} }
/** ISR to manage the reception of bits to the software UART. */ /** ISR to manage the reception of bits to the software UART. */
ISR(TIMER1_CAPT_vect, ISR_BLOCK) ISR(TIMER1_COMPA_vect, ISR_BLOCK)
{ {
/* Cache the current RX pin value for later checking */ /* Cache the current RX pin value for later checking */
uint8_t SRX_Cached = (SRXPIN & (1 << SRX)); uint8_t SRX_Cached = (SRXPIN & (1 << SRX));
@ -125,7 +125,7 @@ ISR(TIMER1_CAPT_vect, ISR_BLOCK)
} }
/** ISR to manage the transmission of bits via the software UART. */ /** ISR to manage the transmission of bits via the software UART. */
ISR(TIMER3_CAPT_vect, ISR_BLOCK) ISR(TIMER3_COMPA_vect, ISR_BLOCK)
{ {
/* Check if transmission has finished */ /* Check if transmission has finished */
if (TX_BitsRemaining) if (TX_BitsRemaining)

@ -60,8 +60,8 @@
{ {
uint16_t BitTime = ((F_CPU / Baud) - 1); uint16_t BitTime = ((F_CPU / Baud) - 1);
ICR1 = BitTime; OCR1A = BitTime;
ICR3 = BitTime; OCR3A = BitTime;
} }
/* Function Prototypes: */ /* Function Prototypes: */

Loading…
Cancel
Save