forksand
/
qmk_firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix error in XMEGA clock platform driver for the DFLL calibration byte order.

Browse Source
pull/1469/head
Dean Camera 13 years ago
parent ab43251bf9
commit c739974292
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File

18
LUFA/Platform/XMEGA/ClockManagement.h
Unescape View File

@ -275,19 +275,19 @@
switch (Source) switch (Source)
{ {
case CLOCK_SRC_INT_RC2MHZ: case CLOCK_SRC_INT_RC2MHZ:
OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp); OSC.DFLLCTRL |= (Reference << OSC_RC2MCREF_bp);
DFLLRC2M.COMP1 = (DFLLCompare >> 8); DFLLRC2M.COMP1 = (DFLLCompare & 0xFF);
DFLLRC2M.COMP2 = (DFLLCompare & 0xFF); DFLLRC2M.COMP2 = (DFLLCompare >> 8);
DFLLRC2M.CALA = (DFFLCal >> 8); DFLLRC2M.CALA = (DFFLCal & 0xFF);
DFLLRC2M.CALB = (DFFLCal & 0xFF); DFLLRC2M.CALB = (DFFLCal >> 8);
DFLLRC2M.CTRL = DFLL_ENABLE_bm; DFLLRC2M.CTRL = DFLL_ENABLE_bm;
break; break;
case CLOCK_SRC_INT_RC32MHZ: case CLOCK_SRC_INT_RC32MHZ:
OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp); OSC.DFLLCTRL |= (Reference << OSC_RC32MCREF_gp);
DFLLRC32M.COMP1 = (DFLLCompare >> 8); DFLLRC32M.COMP1 = (DFLLCompare & 0xFF);
DFLLRC32M.COMP2 = (DFLLCompare & 0xFF); DFLLRC32M.COMP2 = (DFLLCompare >> 8);
DFLLRC32M.CALA = (DFFLCal >> 8); DFLLRC32M.CALA = (DFFLCal & 0xFF);
DFLLRC32M.CALB = (DFFLCal & 0xFF); DFLLRC32M.CALB = (DFFLCal >> 8);
DFLLRC32M.CTRL = DFLL_ENABLE_bm; DFLLRC32M.CTRL = DFLL_ENABLE_bm;
break; break;
default: default:

Write Preview
Loading…
Cancel
Save