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@ -61,7 +61,11 @@
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* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models
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* set to an appropriate ADC channel number in the project makefile for VTARGET detection to operate correctly. On models
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* without an ADC converter, VTARGET will report at a fixed 5V level.
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* without an ADC converter, VTARGET will report at a fixed 5V level.
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*
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*
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* Connections to the device are simple for SPI programming:
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* When compiled for the XPLAIN board target, this will automatically configure itself for the correct connections to the
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* XPLAIN's XMEGA AVR, and will enable only PDI programming support.
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*
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*
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* Connections to the device for SPI programming (when enabled):
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*
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*
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* <table>
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* <table>
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* <tr>
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* <tr>
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@ -105,7 +109,7 @@
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* <b><sup>2</sup></b> <i>See \ref SSec_Options section</i>
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* <b><sup>2</sup></b> <i>See \ref SSec_Options section</i>
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*
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*
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*
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*
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* Connections to the device are simple for SPI programming:
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* Connections to the device for PDI programming (when enabled):
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*
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*
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* <table>
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* <table>
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* <tr>
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* <tr>
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@ -158,19 +162,20 @@
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* <tr>
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* <tr>
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* <td>RESET_LINE_PORT</td>
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* <td>RESET_LINE_PORT</td>
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>PORT register for the programmer's target RESET line.</td>
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* <td>PORT register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* </tr>
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* <tr>
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* <tr>
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* <td>RESET_LINE_DDR</td>
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* <td>RESET_LINE_DDR</td>
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>DDR register for the programmer's target RESET line.</td>
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* <td>DDR register for the programmer's target RESET line. <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* </tr>
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* <tr>
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* <tr>
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* <td>RESET_LINE_MASK</td>
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* <td>RESET_LINE_MASK</td>
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the
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* <td>Mask for the programmer's target RESET line on the chosen port. <b>Must not be the AVR's /SS pin</b>, as the
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* target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the
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* target pins are tri-stated when not in use, and low signals on the /SS pin will force SPI slave mode when the
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* pin is configured as an input. When in PDI programming mode, this is the target clock pin.</td>
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* pin is configured as an input. When in PDI programming mode, this is the target clock pin.
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* <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* </tr>
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* <tr>
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* <tr>
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* <td>VTARGET_ADC_CHANNEL</td>
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* <td>VTARGET_ADC_CHANNEL</td>
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@ -180,12 +185,12 @@
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* <tr>
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* <tr>
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* <td>ENABLE_SPI_PROTOCOL</td>
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* <td>ENABLE_SPI_PROTOCOL</td>
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>Define to enable SPI programming protocol support.</td>
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* <td>Define to enable SPI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* </tr>
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* <tr>
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* <tr>
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* <td>ENABLE_XPROG_PROTOCOL</td>
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* <td>ENABLE_XPROG_PROTOCOL</td>
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* <td>Makefile CDEFS</td>
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* <td>Makefile CDEFS</td>
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* <td>Define to enable XMEGA PDI programming protocol support.</td>
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* <td>Define to enable XMEGA PDI programming protocol support. <i>Ignored when compiled for the XPLAIN board.</i></td>
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* </tr>
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* </tr>
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* </table>
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* </table>
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*/
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*/
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