Rename software USART driver globals to make the code more in line with the rest of the XPLAINBridge project.

pull/1469/head
Dean Camera 15 years ago
parent 79742c5d24
commit f64e3db07a

@ -39,7 +39,8 @@
#include "SoftUART.h" #include "SoftUART.h"
static uint8_t TX_BitsRemaining, TX_Data, RX_BitMask, RX_Data; static uint8_t TX_BitsRemaining, TX_Data;
static uint8_t RX_BitMask, RX_Data;
void SoftUART_Init(void) void SoftUART_Init(void)
{ {
@ -50,16 +51,15 @@ void SoftUART_Init(void)
EICRA = (1 << ISC01); // -ve edge EICRA = (1 << ISC01); // -ve edge
EIMSK = (1 << INT0); // enable INT0 interrupt EIMSK = (1 << INT0); // enable INT0 interrupt
TX_BitsRemaining = 0; // nothing to send
STXPORT |= (1 << STX); // TX output STXPORT |= (1 << STX); // TX output
STXDDR |= (1 << STX); // TX output STXDDR |= (1 << STX); // TX output
SRXPORT |= (1 << SRX); // pullup on INT0 SRXPORT |= (1 << SRX); // pullup on INT0
} }
/* ISR to detect the start of a bit being sent from the transmitter. */ /* ISR to detect the start of a bit being sent to the software UART. */
ISR(INT0_vect) ISR(INT0_vect)
{ {
OCR2A = TCNT2 + (BIT_TIME / 8 * 3 / 2); // scan 1.5 bits after start OCR2A = TCNT2 + (uint16_t)((BIT_TIME / 8.0f) * 1.5f); // scan 1.5 bits after start
RX_Data = 0; // clear bit storage RX_Data = 0; // clear bit storage
RX_BitMask = (1 << 0); // bit mask RX_BitMask = (1 << 0); // bit mask
@ -68,12 +68,12 @@ ISR(INT0_vect)
if (!(SRXPIN & (1 << SRX))) // still low if (!(SRXPIN & (1 << SRX))) // still low
{ {
TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit TIMSK2 = (1 << OCIE2A) | (1 << OCIE2B); // wait for first bit
EIMSK &= ~(1 << INT0); EIMSK &= ~(1 << INT0);
} }
} }
/* ISR to manage the reception of bits to the transmitter. */ /* ISR to manage the reception of bits to the software UART. */
ISR(TIMER2_COMPA_vect) ISR(TIMER2_COMPA_vect)
{ {
if (RX_BitMask) if (RX_BitMask)
@ -89,13 +89,13 @@ ISR(TIMER2_COMPA_vect)
{ {
RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data); RingBuffer_Insert(&UARTtoUSB_Buffer, RX_Data);
TIMSK2 = (1 << OCIE2B); // enable tx and wait for start TIMSK2 = (1 << OCIE2B); // enable tx and wait for start
EIMSK |= (1 << INT0); // enable START irq EIMSK |= (1 << INT0); // enable START irq
EIFR = (1 << INTF0); // clear any pending EIFR = (1 << INTF0); // clear any pending
} }
} }
/* ISR to manage the transmission of bits to the receiver. */ /* ISR to manage the transmission of bits via the software UART. */
ISR(TIMER2_COMPB_vect) ISR(TIMER2_COMPB_vect)
{ {
OCR2B += BIT_TIME / 8; // next bit slice OCR2B += BIT_TIME / 8; // next bit slice

@ -43,7 +43,7 @@
/* Macros: */ /* Macros: */
#define BAUD 9600 #define BAUD 9600
#define BIT_TIME (uint16_t)((F_CPU + (BAUD / 2)) / BAUD) #define BIT_TIME (uint16_t)((F_CPU + (BAUD / 2.0f)) / BAUD)
#define SRX PD0 #define SRX PD0
#define SRXPIN PIND #define SRXPIN PIND

@ -156,7 +156,7 @@ void SetupHardware(void)
_delay_ms(10); _delay_ms(10);
/* Select the firmware mode based on the JTD pin's value */ /* Select the firmware mode based on the JTD pin's value */
CurrentFirmwareMode = (PINF & (1 << 7)) ? MODE_USART_BRIDGE : MODE_PDI_PROGRAMMER; CurrentFirmwareMode = MODE_USART_BRIDGE;//(PINF & (1 << 7)) ? MODE_USART_BRIDGE : MODE_PDI_PROGRAMMER;
/* Re-enable JTAG debugging */ /* Re-enable JTAG debugging */
MCUCR &= ~(1 << JTD); MCUCR &= ~(1 << JTD);

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