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165 lines
7.2 KiB
165 lines
7.2 KiB
3 years ago
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/*!
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\file gd32vf103_exmc.c
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\brief EXMC driver
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\version 2019-06-05, V1.0.0, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32vf103_exmc.h"
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/* EXMC bank0 register reset value */
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#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU)
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#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
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/* EXMC register bit offset */
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#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
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#define SNCTL_WREN_OFFSET ((uint32_t)12U)
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#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
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#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
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#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
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#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
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#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
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/*!
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\brief deinitialize EXMC NOR/SRAM region
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\param[in] norsram_region: select the region of bank0
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\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
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\param[out] none
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\retval none
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*/
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void exmc_norsram_deinit(uint32_t norsram_region)
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{
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/* reset the registers */
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if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){
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EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET;
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}
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EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET;
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}
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/*!
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\brief initialize the structure exmc_norsram_parameter_struct
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\param[in] none
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\param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer
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\retval none
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*/
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void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
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{
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/* configure the structure with default value */
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exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
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exmc_norsram_init_struct->address_data_mux = ENABLE;
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exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
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exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
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exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
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exmc_norsram_init_struct->memory_write = ENABLE;
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exmc_norsram_init_struct->nwait_signal = ENABLE;
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exmc_norsram_init_struct->asyn_wait = DISABLE;
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/* read/write timing configure */
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exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
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exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
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exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
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exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
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}
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/*!
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\brief initialize EXMC NOR/SRAM region
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\param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
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norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0
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asyn_wait: ENABLE or DISABLE
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nwait_signal: ENABLE or DISABLE
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memory_write: ENABLE or DISABLE
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nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
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databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
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memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
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address_data_mux: ENABLE
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read_write_timing: structure exmc_norsram_timing_parameter_struct set the time
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\param[out] none
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\retval none
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*/
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void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
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{
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uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U;
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/* get the register value */
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snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
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/* clear relative bits */
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snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL |
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EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX));
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snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
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exmc_norsram_init_struct->memory_type |
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exmc_norsram_init_struct->databus_width |
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exmc_norsram_init_struct->nwait_polarity |
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(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
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(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
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(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET);
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sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
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(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
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(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
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(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT );
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/* nor flash access enable */
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if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
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snctl |= (uint32_t)EXMC_SNCTL_NREN;
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}
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/* configure the registers */
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EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
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EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
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}
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/*!
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\brief enable EXMC NOR/PSRAM bank region
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\param[in] norsram_region: specify the region of NOR/PSRAM bank
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\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
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\param[out] none
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\retval none
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*/
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void exmc_norsram_enable(uint32_t norsram_region)
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{
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EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
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}
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/*!
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\brief disable EXMC NOR/PSRAM bank region
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\param[in] norsram_region: specify the region of NOR/PSRAM bank
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\arg EXMC_BANK0_NORSRAM_REGIONx(x=0)
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\param[out] none
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\retval none
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*/
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void exmc_norsram_disable(uint32_t norsram_region)
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{
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EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
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}
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