Ivan Olenichev
3 months ago
44 changed files with 18203 additions and 0 deletions
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/*!
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\file gd32vf103_adc.h |
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\brief definitions for the ADC |
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\version 2019-06-05, V1.0.0, firmware for GD32VF103 |
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*/ |
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc. |
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Redistribution and use in source and binary forms, with or without modification, |
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are permitted provided that the following conditions are met: |
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1. Redistributions of source code must retain the above copyright notice, this |
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list of conditions and the following disclaimer. |
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2. Redistributions in binary form must reproduce the above copyright notice, |
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this list of conditions and the following disclaimer in the documentation |
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and/or other materials provided with the distribution. |
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3. Neither the name of the copyright holder nor the names of its contributors |
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may be used to endorse or promote products derived from this software without |
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specific prior written permission. |
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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OF SUCH DAMAGE. |
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*/ |
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#ifndef GD32VF103_ADC_H |
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#define GD32VF103_ADC_H |
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#include "gd32vf103.h" |
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/* ADC definitions */ |
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#define ADC0 ADC_BASE |
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#define ADC1 (ADC_BASE + 0x400U) |
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/* registers definitions */ |
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#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ |
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#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ |
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#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ |
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#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ |
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#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ |
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#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ |
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#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ |
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#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ |
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#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ |
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#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ |
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#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ |
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#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ |
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#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ |
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#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ |
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#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ |
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#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ |
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#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ |
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#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ |
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#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ |
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#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ |
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#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */ |
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/* bits definitions */ |
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/* ADC_STAT */ |
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#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ |
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#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ |
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#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ |
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#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ |
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#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ |
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/* ADC_CTL0 */ |
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#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ |
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#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ |
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#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ |
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#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ |
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#define ADC_CTL0_SM BIT(8) /*!< scan mode */ |
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#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ |
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#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ |
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#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ |
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#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ |
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#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ |
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#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ |
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#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ |
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#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ |
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/* ADC_CTL1 */ |
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#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ |
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#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ |
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#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ |
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#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ |
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#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ |
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#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ |
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#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ |
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#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ |
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#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ |
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#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ |
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#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ |
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#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ |
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#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ |
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/* ADC_SAMPTx x=0..1 */ |
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#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ |
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/* ADC_IOFFx x=0..3 */ |
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#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ |
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/* ADC_WDHT */ |
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#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ |
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/* ADC_WDLT */ |
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#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ |
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/* ADC_RSQx x=0..2 */ |
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#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ |
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#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ |
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/* ADC_ISQ */ |
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#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ |
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#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ |
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/* ADC_IDATAx x=0..3*/ |
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#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ |
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/* ADC_RDATA */ |
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#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ |
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#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ |
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/* ADC_OVSCR */ |
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#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ |
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#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ |
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#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ |
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#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ |
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#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ |
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/* constants definitions */ |
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/* adc_stat register value */ |
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#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ |
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#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ |
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#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ |
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#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ |
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#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ |
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/* adc_ctl0 register value */ |
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#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ |
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/* scan mode */ |
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#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ |
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/* inserted channel group convert automatically */ |
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#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ |
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/* ADC sync mode */ |
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#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ |
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#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ |
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#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ |
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#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ |
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#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ |
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#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ |
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#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ |
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#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ |
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#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ |
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#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ |
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#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ |
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/* adc_ctl1 register value */ |
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#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ |
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#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ |
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/* continuous mode */ |
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#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ |
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/* external trigger select for regular channel */ |
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#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ |
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/* for ADC0 and ADC1 regular channel */ |
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ |
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#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ |
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#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ |
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/* external trigger mode for inserted channel */ |
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#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ |
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/* for ADC0 and ADC1 inserted channel */ |
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#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ |
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#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ |
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#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ |
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/* adc_samptx register value */ |
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#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ |
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#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ |
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#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ |
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#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ |
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#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ |
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#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ |
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#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ |
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#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ |
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#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ |
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/* adc_ioffx register value */ |
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#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ |
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/* adc_wdht register value */ |
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#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ |
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/* adc_wdlt register value */ |
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#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ |
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/* adc_rsqx register value */ |
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#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ |
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/* adc_isq register value */ |
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#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ |
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/* ADC channel group definitions */ |
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#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ |
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#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ |
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#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ |
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#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ |
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/* ADC inserted channel definitions */ |
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#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ |
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#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ |
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#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ |
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#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ |
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/* ADC channel definitions */ |
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#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ |
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#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ |
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#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ |
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#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ |
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#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ |
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#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ |
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#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ |
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#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ |
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#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ |
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#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ |
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#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ |
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#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ |
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#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ |
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#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ |
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#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ |
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#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ |
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#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ |
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#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ |
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/* ADC interrupt */ |
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#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ |
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#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ |
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#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ |
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/* ADC interrupt flag */ |
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#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ |
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#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ |
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#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ |
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/* ADC resolution definitions */ |
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#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) |
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#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ |
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#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ |
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#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ |
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#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */ |
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/* ADC oversampling mode */ |
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#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */ |
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#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ |
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/* ADC oversampling shift */ |
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#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) |
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#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */ |
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#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ |
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/* ADC oversampling ratio */ |
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#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) |
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#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */ |
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#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */ |
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/* function declarations */ |
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/* initialization config */ |
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/* reset ADC */ |
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void adc_deinit(uint32_t adc_periph); |
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/* configure the ADC sync mode */ |
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void adc_mode_config(uint32_t mode); |
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/* enable or disable ADC special function */ |
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void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); |
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/* configure ADC data alignment */ |
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void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); |
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/* enable ADC interface */ |
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void adc_enable(uint32_t adc_periph); |
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/* disable ADC interface */ |
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void adc_disable(uint32_t adc_periph); |
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/* ADC calibration and reset calibration */ |
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void adc_calibration_enable(uint32_t adc_periph); |
|||
/* enable the temperature sensor and Vrefint channel */ |
|||
void adc_tempsensor_vrefint_enable(void); |
|||
/* disable the temperature sensor and Vrefint channel */ |
|||
void adc_tempsensor_vrefint_disable(void); |
|||
|
|||
/* DMA config */ |
|||
/* enable DMA request */ |
|||
void adc_dma_mode_enable(uint32_t adc_periph); |
|||
/* disable DMA request */ |
|||
void adc_dma_mode_disable(uint32_t adc_periph); |
|||
|
|||
/* regular group and inserted group config */ |
|||
/* configure ADC discontinuous mode */ |
|||
void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); |
|||
|
|||
/* configure the length of regular channel group or inserted channel group */ |
|||
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); |
|||
/* configure ADC regular channel */ |
|||
void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); |
|||
/* configure ADC inserted channel */ |
|||
void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); |
|||
/* configure ADC inserted channel offset */ |
|||
void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); |
|||
|
|||
/* configure ADC external trigger source */ |
|||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); |
|||
/* configure ADC external trigger */ |
|||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); |
|||
/* enable ADC software trigger */ |
|||
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); |
|||
|
|||
/* get channel data */ |
|||
/* read ADC regular group data register */ |
|||
uint16_t adc_regular_data_read(uint32_t adc_periph); |
|||
/* read ADC inserted group data register */ |
|||
uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); |
|||
/* read the last ADC0 and ADC1 conversion result data in sync mode */ |
|||
uint32_t adc_sync_mode_convert_value_read(void); |
|||
|
|||
/* watchdog config */ |
|||
/* configure ADC analog watchdog single channel */ |
|||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); |
|||
/* configure ADC analog watchdog group channel */ |
|||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); |
|||
/* disable ADC analog watchdog */ |
|||
void adc_watchdog_disable(uint32_t adc_periph); |
|||
/* configure ADC analog watchdog threshold */ |
|||
void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); |
|||
|
|||
/* interrupt & flag functions */ |
|||
/* get the ADC flag bits */ |
|||
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); |
|||
/* clear the ADC flag bits */ |
|||
void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); |
|||
/* get the bit state of ADCx software start conversion */ |
|||
FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); |
|||
/* get the bit state of ADCx software inserted channel start conversion */ |
|||
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); |
|||
/* get the ADC interrupt bits */ |
|||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); |
|||
/* clear the ADC flag */ |
|||
void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); |
|||
/* enable ADC interrupt */ |
|||
void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); |
|||
/* disable ADC interrupt */ |
|||
void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); |
|||
|
|||
/* ADC resolution & oversample */ |
|||
/* ADC resolution config */ |
|||
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); |
|||
/* ADC oversample mode config */ |
|||
void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); |
|||
/* enable ADC oversample mode */ |
|||
void adc_oversample_mode_enable(uint32_t adc_periph); |
|||
/* disable ADC oversample mode */ |
|||
void adc_oversample_mode_disable(uint32_t adc_periph); |
|||
|
|||
#endif /* GD32VF103_ADC_H */ |
|||
@ -0,0 +1,227 @@ |
|||
/*!
|
|||
\file gd32vf103_bkp.h |
|||
\brief definitions for the BKP |
|||
|
|||
\version 2019-06-05, V1.0.0, firmware for GD32VF103 |
|||
*/ |
|||
|
|||
/*
|
|||
Copyright (c) 2019, GigaDevice Semiconductor Inc. |
|||
|
|||
Redistribution and use in source and binary forms, with or without modification, |
|||
are permitted provided that the following conditions are met: |
|||
|
|||
1. Redistributions of source code must retain the above copyright notice, this |
|||
list of conditions and the following disclaimer. |
|||
2. Redistributions in binary form must reproduce the above copyright notice, |
|||
this list of conditions and the following disclaimer in the documentation |
|||
and/or other materials provided with the distribution. |
|||
3. Neither the name of the copyright holder nor the names of its contributors |
|||
may be used to endorse or promote products derived from this software without |
|||
specific prior written permission. |
|||
|
|||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
|||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
|||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
|||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
|||
OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef GD32VF103_BKP_H |
|||
#define GD32VF103_BKP_H |
|||
|
|||
#include "gd32vf103.h" |
|||
|
|||
/* BKP definitions */ |
|||
#define BKP BKP_BASE /*!< BKP base address */ |
|||
|
|||
/* registers definitions */ |
|||
#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ |
|||
#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ |
|||
#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ |
|||
#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ |
|||
#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ |
|||
#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ |
|||
#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ |
|||
#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ |
|||
#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ |
|||
#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ |
|||
#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ |
|||
#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ |
|||
#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ |
|||
#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ |
|||
#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ |
|||
#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ |
|||
#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ |
|||
#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ |
|||
#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ |
|||
#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ |
|||
#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ |
|||
#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ |
|||
#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ |
|||
#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ |
|||
#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ |
|||
#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ |
|||
#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ |
|||
#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ |
|||
#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ |
|||
#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ |
|||
#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ |
|||
#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ |
|||
#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ |
|||
#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ |
|||
#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ |
|||
#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ |
|||
#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ |
|||
#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ |
|||
#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ |
|||
#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ |
|||
#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ |
|||
#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ |
|||
#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ |
|||
#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ |
|||
#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ |
|||
|
|||
/* bits definitions */ |
|||
/* BKP_DATA */ |
|||
#define BKP_DATA BITS(0,15) /*!< backup data */ |
|||
|
|||
/* BKP_OCTL */ |
|||
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ |
|||
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ |
|||
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ |
|||
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ |
|||
|
|||
/* BKP_TPCTL */ |
|||
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ |
|||
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ |
|||
|
|||
/* BKP_TPCS */ |
|||
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ |
|||
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ |
|||
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ |
|||
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ |
|||
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ |
|||
|
|||
/* constants definitions */ |
|||
/* BKP data register number */ |
|||
typedef enum |
|||
{ |
|||
BKP_DATA_0 = 1, /*!< BKP data register 0 */ |
|||
BKP_DATA_1, /*!< BKP data register 1 */ |
|||
BKP_DATA_2, /*!< BKP data register 2 */ |
|||
BKP_DATA_3, /*!< BKP data register 3 */ |
|||
BKP_DATA_4, /*!< BKP data register 4 */ |
|||
BKP_DATA_5, /*!< BKP data register 5 */ |
|||
BKP_DATA_6, /*!< BKP data register 6 */ |
|||
BKP_DATA_7, /*!< BKP data register 7 */ |
|||
BKP_DATA_8, /*!< BKP data register 8 */ |
|||
BKP_DATA_9, /*!< BKP data register 9 */ |
|||
BKP_DATA_10, /*!< BKP data register 10 */ |
|||
BKP_DATA_11, /*!< BKP data register 11 */ |
|||
BKP_DATA_12, /*!< BKP data register 12 */ |
|||
BKP_DATA_13, /*!< BKP data register 13 */ |
|||
BKP_DATA_14, /*!< BKP data register 14 */ |
|||
BKP_DATA_15, /*!< BKP data register 15 */ |
|||
BKP_DATA_16, /*!< BKP data register 16 */ |
|||
BKP_DATA_17, /*!< BKP data register 17 */ |
|||
BKP_DATA_18, /*!< BKP data register 18 */ |
|||
BKP_DATA_19, /*!< BKP data register 19 */ |
|||
BKP_DATA_20, /*!< BKP data register 20 */ |
|||
BKP_DATA_21, /*!< BKP data register 21 */ |
|||
BKP_DATA_22, /*!< BKP data register 22 */ |
|||
BKP_DATA_23, /*!< BKP data register 23 */ |
|||
BKP_DATA_24, /*!< BKP data register 24 */ |
|||
BKP_DATA_25, /*!< BKP data register 25 */ |
|||
BKP_DATA_26, /*!< BKP data register 26 */ |
|||
BKP_DATA_27, /*!< BKP data register 27 */ |
|||
BKP_DATA_28, /*!< BKP data register 28 */ |
|||
BKP_DATA_29, /*!< BKP data register 29 */ |
|||
BKP_DATA_30, /*!< BKP data register 30 */ |
|||
BKP_DATA_31, /*!< BKP data register 31 */ |
|||
BKP_DATA_32, /*!< BKP data register 32 */ |
|||
BKP_DATA_33, /*!< BKP data register 33 */ |
|||
BKP_DATA_34, /*!< BKP data register 34 */ |
|||
BKP_DATA_35, /*!< BKP data register 35 */ |
|||
BKP_DATA_36, /*!< BKP data register 36 */ |
|||
BKP_DATA_37, /*!< BKP data register 37 */ |
|||
BKP_DATA_38, /*!< BKP data register 38 */ |
|||
BKP_DATA_39, /*!< BKP data register 39 */ |
|||
BKP_DATA_40, /*!< BKP data register 40 */ |
|||
BKP_DATA_41, /*!< BKP data register 41 */ |
|||
}bkp_data_register_enum; |
|||
|
|||
/* BKP register */ |
|||
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) |
|||
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) |
|||
|
|||
/* get data of BKP data register */ |
|||
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) |
|||
|
|||
/* RTC clock calibration value */ |
|||
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) |
|||
|
|||
/* RTC output selection */ |
|||
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ |
|||
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ |
|||
|
|||
/* tamper pin active level */ |
|||
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ |
|||
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ |
|||
|
|||
/* tamper flag */ |
|||
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ |
|||
|
|||
/* tamper interrupt flag */ |
|||
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ |
|||
|
|||
/* function declarations */ |
|||
/* reset BKP registers */ |
|||
void bkp_deinit(void); |
|||
/* write BKP data register */ |
|||
void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); |
|||
/* read BKP data register */ |
|||
uint16_t bkp_data_read(bkp_data_register_enum register_number); |
|||
|
|||
/* RTC related functions */ |
|||
/* enable RTC clock calibration output */ |
|||
void bkp_rtc_calibration_output_enable(void); |
|||
/* disable RTC clock calibration output */ |
|||
void bkp_rtc_calibration_output_disable(void); |
|||
/* enable RTC alarm or second signal output */ |
|||
void bkp_rtc_signal_output_enable(void); |
|||
/* disable RTC alarm or second signal output */ |
|||
void bkp_rtc_signal_output_disable(void); |
|||
/* select RTC output */ |
|||
void bkp_rtc_output_select(uint16_t outputsel); |
|||
/* set RTC clock calibration value */ |
|||
void bkp_rtc_calibration_value_set(uint8_t value); |
|||
|
|||
/* tamper pin related functions */ |
|||
/* enable tamper pin detection */ |
|||
void bkp_tamper_detection_enable(void); |
|||
/* disable tamper pin detection */ |
|||
void bkp_tamper_detection_disable(void); |
|||
/* set tamper pin active level */ |
|||
void bkp_tamper_active_level_set(uint16_t level); |
|||
|
|||
/* interrupt & flag functions */ |
|||
/* enable tamper interrupt */ |
|||
void bkp_interrupt_enable(void); |
|||
/* disable tamper interrupt */ |
|||
void bkp_interrupt_disable(void); |
|||
/* get tamper flag state */ |
|||
FlagStatus bkp_flag_get(void); |
|||
/* clear tamper flag state */ |
|||
void bkp_flag_clear(void); |
|||
/* get tamper interrupt flag state */ |
|||
FlagStatus bkp_interrupt_flag_get(void); |
|||
/* clear tamper interrupt flag state */ |
|||
void bkp_interrupt_flag_clear(void); |
|||
|
|||
#endif /* GD32VF103_BKP_H */ |
|||
@ -0,0 +1,751 @@ |
|||
/*!
|
|||
\file gd32vf103_can.h |
|||
\brief definitions for the CAN |
|||
|
|||
\version 2019-06-05, V1.0.0, firmware for GD32VF103 |
|||
\version 2019-11-27, V1.0.1, firmware for GD32VF103 |
|||
*/ |
|||
|
|||
/*
|
|||
Copyright (c) 2019, GigaDevice Semiconductor Inc. |
|||
|
|||
Redistribution and use in source and binary forms, with or without modification, |
|||
are permitted provided that the following conditions are met: |
|||
|
|||
1. Redistributions of source code must retain the above copyright notice, this |
|||
list of conditions and the following disclaimer. |
|||
2. Redistributions in binary form must reproduce the above copyright notice, |
|||
this list of conditions and the following disclaimer in the documentation |
|||
and/or other materials provided with the distribution. |
|||
3. Neither the name of the copyright holder nor the names of its contributors |
|||
may be used to endorse or promote products derived from this software without |
|||
specific prior written permission. |
|||
|
|||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
|||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
|||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
|||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
|||
OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef GD32VF103_CAN_H |
|||
#define GD32VF103_CAN_H |
|||
|
|||
#include "gd32vf103.h" |
|||
|
|||
/* CAN definitions */ |
|||
#define CAN0 CAN_BASE /*!< CAN0 base address */ |
|||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ |
|||
|
|||
/* registers definitions */ |
|||
#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ |
|||
#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ |
|||
#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ |
|||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ |
|||
#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ |
|||
#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ |
|||
#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ |
|||
#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ |
|||
#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ |
|||
#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ |
|||
#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ |
|||
#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ |
|||
#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ |
|||
#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ |
|||
#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ |
|||
#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ |
|||
#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ |
|||
#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ |
|||
#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ |
|||
#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ |
|||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ |
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#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ |
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#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ |
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#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ |
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#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ |
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#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ |
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#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ |
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#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ |
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#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ |
|||
#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ |
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#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ |
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#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ |
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#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ |
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#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ |
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#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ |
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#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ |
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#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ |
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#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ |
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#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ |
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#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ |
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#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ |
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#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ |
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#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ |
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#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ |
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#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ |
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#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ |
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#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ |
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#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ |
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#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ |
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#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ |
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#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ |
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#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ |
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#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ |
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#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ |
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#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ |
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#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ |
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#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ |
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#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ |
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#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ |
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#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ |
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#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ |
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#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ |
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#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ |
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#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ |
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#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ |
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#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ |
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#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ |
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#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ |
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#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ |
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#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ |
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#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ |
|||
#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ |
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#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ |
|||
#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ |
|||
#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ |
|||
#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ |
|||
#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ |
|||
#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ |
|||
#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ |
|||
#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ |
|||
#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ |
|||
#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ |
|||
#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ |
|||
#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ |
|||
#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ |
|||
#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ |
|||
#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ |
|||
#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ |
|||
#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ |
|||
|
|||
/* CAN transmit mailbox bank */ |
|||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ |
|||
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ |
|||
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ |
|||
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ |
|||
|
|||
/* CAN filter bank */ |
|||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ |
|||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ |
|||
|
|||
/* CAN receive fifo mailbox bank */ |
|||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ |
|||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ |
|||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ |
|||
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ |
|||
|
|||
/* bits definitions */ |
|||
/* CAN_CTL */ |
|||
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ |
|||
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ |
|||
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ |
|||
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ |
|||
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ |
|||
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ |
|||
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ |
|||
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ |
|||
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ |
|||
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ |
|||
|
|||
/* CAN_STAT */ |
|||
#define CAN_STAT_IWS BIT(0) /*!< initial working state */ |
|||
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ |
|||
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ |
|||
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ |
|||
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ |
|||
#define CAN_STAT_TS BIT(8) /*!< transmitting state */ |
|||
#define CAN_STAT_RS BIT(9) /*!< receiving state */ |
|||
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ |
|||
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ |
|||
|
|||
/* CAN_TSTAT */ |
|||
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ |
|||
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ |
|||
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ |
|||
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ |
|||
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ |
|||
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ |
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#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ |
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#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ |
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#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ |
|||
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ |
|||
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ |
|||
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ |
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#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ |
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#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ |
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#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ |
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#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ |
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#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ |
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#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ |
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#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ |
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#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ |
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#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ |
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#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ |
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|
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/* CAN_RFIFO0 */ |
|||
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ |
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#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ |
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#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ |
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#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ |
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|
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/* CAN_RFIFO1 */ |
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#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ |
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#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ |
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#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ |
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#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ |
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|
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/* CAN_INTEN */ |
|||
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ |
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#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ |
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#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ |
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#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ |
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#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ |
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#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ |
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#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ |
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#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ |
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#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ |
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#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ |
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#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ |
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#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ |
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#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ |
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#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ |
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|
|||
/* CAN_ERR */ |
|||
#define CAN_ERR_WERR BIT(0) /*!< warning error */ |
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#define CAN_ERR_PERR BIT(1) /*!< passive error */ |
|||
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ |
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#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ |
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#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ |
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#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ |
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|
|||
/* CAN_BT */ |
|||
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ |
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#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ |
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#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ |
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#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ |
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#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ |
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#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ |
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|
|||
/* CAN_TMIx */ |
|||
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ |
|||
#define CAN_TMI_FT BIT(1) /*!< frame type */ |
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#define CAN_TMI_FF BIT(2) /*!< frame format */ |
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#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ |
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#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ |
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|
|||
/* CAN_TMPx */ |
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#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ |
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#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ |
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#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ |
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|
|||
/* CAN_TMDATA0x */ |
|||
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ |
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#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ |
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#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ |
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#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ |
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|
|||
/* CAN_TMDATA1x */ |
|||
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ |
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#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ |
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#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ |
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#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ |
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|
|||
/* CAN_RFIFOMIx */ |
|||
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ |
|||
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ |
|||
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ |
|||
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ |
|||
|
|||
/* CAN_RFIFOMPx */ |
|||
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ |
|||
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ |
|||
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ |
|||
|
|||
/* CAN_RFIFOMDATA0x */ |
|||
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ |
|||
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ |
|||
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ |
|||
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ |
|||
|
|||
/* CAN_RFIFOMDATA1x */ |
|||
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ |
|||
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ |
|||
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ |
|||
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ |
|||
|
|||
/* CAN_FCTL */ |
|||
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ |
|||
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ |
|||
|
|||
/* CAN_FMCFG */ |
|||
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ |
|||
|
|||
/* CAN_FSCFG */ |
|||
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ |
|||
|
|||
/* CAN_FAFIFO */ |
|||
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ |
|||
|
|||
/* CAN_FW */ |
|||
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ |
|||
|
|||
/* CAN_FxDATAy */ |
|||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ |
|||
|
|||
/* consts definitions */ |
|||
/* define the CAN bit position and its register index offset */ |
|||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) |
|||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) |
|||
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) |
|||
|
|||
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) |
|||
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) |
|||
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) |
|||
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) |
|||
|
|||
/* register offset */ |
|||
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ |
|||
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ |
|||
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ |
|||
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ |
|||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ |
|||
|
|||
/* CAN flags */ |
|||
typedef enum |
|||
{ |
|||
/* flags in STAT register */ |
|||
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ |
|||
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ |
|||
CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ |
|||
CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ |
|||
CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ |
|||
CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ |
|||
CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ |
|||
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ |
|||
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ |
|||
/* flags in TSTAT register */ |
|||
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ |
|||
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ |
|||
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ |
|||
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ |
|||
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ |
|||
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ |
|||
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ |
|||
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ |
|||
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ |
|||
CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ |
|||
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ |
|||
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ |
|||
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ |
|||
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ |
|||
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ |
|||
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ |
|||
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ |
|||
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ |
|||
/* flags in RFIFO0 register */ |
|||
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ |
|||
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ |
|||
/* flags in RFIFO1 register */ |
|||
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ |
|||
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ |
|||
/* flags in ERR register */ |
|||
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ |
|||
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ |
|||
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ |
|||
}can_flag_enum; |
|||
|
|||
/* CAN interrupt flags */ |
|||
typedef enum |
|||
{ |
|||
/* interrupt flags in STAT register */ |
|||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ |
|||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ |
|||
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ |
|||
/* interrupt flags in TSTAT register */ |
|||
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ |
|||
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ |
|||
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ |
|||
/* interrupt flags in RFIFO0 register */ |
|||
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ |
|||
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ |
|||
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ |
|||
/* interrupt flags in RFIFO0 register */ |
|||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ |
|||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ |
|||
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ |
|||
/* interrupt flags in ERR register */ |
|||
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ |
|||
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ |
|||
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ |
|||
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ |
|||
}can_interrupt_flag_enum; |
|||
|
|||
/* CAN initiliaze parameters struct */ |
|||
typedef struct |
|||
{ |
|||
uint8_t working_mode; /*!< CAN working mode */ |
|||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ |
|||
uint8_t time_segment_1; /*!< time segment 1 */ |
|||
uint8_t time_segment_2; /*!< time segment 2 */ |
|||
ControlStatus time_triggered; /*!< time triggered communication mode */ |
|||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ |
|||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */ |
|||
ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ |
|||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ |
|||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */ |
|||
uint16_t prescaler; /*!< baudrate prescaler */ |
|||
}can_parameter_struct; |
|||
|
|||
/* CAN transmit message struct */ |
|||
typedef struct |
|||
{ |
|||
uint32_t tx_sfid; /*!< standard format frame identifier */ |
|||
uint32_t tx_efid; /*!< extended format frame identifier */ |
|||
uint8_t tx_ff; /*!< format of frame, standard or extended format */ |
|||
uint8_t tx_ft; /*!< type of frame, data or remote */ |
|||
uint8_t tx_dlen; /*!< data length */ |
|||
uint8_t tx_data[8]; /*!< transmit data */ |
|||
}can_trasnmit_message_struct; |
|||
|
|||
/* CAN receive message struct */ |
|||
typedef struct |
|||
{ |
|||
uint32_t rx_sfid; /*!< standard format frame identifier */ |
|||
uint32_t rx_efid; /*!< extended format frame identifier */ |
|||
uint8_t rx_ff; /*!< format of frame, standard or extended format */ |
|||
uint8_t rx_ft; /*!< type of frame, data or remote */ |
|||
uint8_t rx_dlen; /*!< data length */ |
|||
uint8_t rx_data[8]; /*!< receive data */ |
|||
uint8_t rx_fi; /*!< filtering index */ |
|||
} can_receive_message_struct; |
|||
|
|||
/* CAN filter parameters struct */ |
|||
typedef struct |
|||
{ |
|||
uint16_t filter_list_high; /*!< filter list number high bits*/ |
|||
uint16_t filter_list_low; /*!< filter list number low bits */ |
|||
uint16_t filter_mask_high; /*!< filter mask number high bits */ |
|||
uint16_t filter_mask_low; /*!< filter mask number low bits */ |
|||
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ |
|||
uint16_t filter_number; /*!< filter number */ |
|||
uint16_t filter_mode; /*!< filter mode, list or mask */ |
|||
uint16_t filter_bits; /*!< filter scale */ |
|||
ControlStatus filter_enable; /*!< filter work or not */ |
|||
}can_filter_parameter_struct; |
|||
|
|||
/* CAN errors */ |
|||
typedef enum |
|||
{ |
|||
CAN_ERROR_NONE = 0, /*!< no error */ |
|||
CAN_ERROR_FILL, /*!< fill error */ |
|||
CAN_ERROR_FORMATE, /*!< format error */ |
|||
CAN_ERROR_ACK, /*!< ACK error */ |
|||
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ |
|||
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ |
|||
CAN_ERROR_CRC, /*!< CRC error */ |
|||
CAN_ERROR_SOFTWARECFG, /*!< software configure */ |
|||
}can_error_enum; |
|||
|
|||
/* transmit states */ |
|||
typedef enum |
|||
{ |
|||
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ |
|||
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ |
|||
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ |
|||
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ |
|||
}can_transmit_state_enum; |
|||
|
|||
typedef enum |
|||
{ |
|||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ |
|||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */ |
|||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ |
|||
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ |
|||
}can_struct_type_enum; |
|||
|
|||
/* CAN baudrate prescaler*/ |
|||
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) |
|||
|
|||
/* CAN bit segment 1*/ |
|||
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) |
|||
|
|||
/* CAN bit segment 2*/ |
|||
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) |
|||
|
|||
/* CAN resynchronization jump width*/ |
|||
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) |
|||
|
|||
/* CAN communication mode*/ |
|||
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) |
|||
|
|||
/* CAN FDATA high 16 bits */ |
|||
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) |
|||
|
|||
/* CAN FDATA low 16 bits */ |
|||
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) |
|||
|
|||
/* CAN1 filter start bank_number*/ |
|||
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) |
|||
|
|||
/* CAN transmit mailbox extended identifier*/ |
|||
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) |
|||
|
|||
/* CAN transmit mailbox standard identifier*/ |
|||
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) |
|||
|
|||
/* transmit data byte 0 */ |
|||
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) |
|||
|
|||
/* transmit data byte 1 */ |
|||
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) |
|||
|
|||
/* transmit data byte 2 */ |
|||
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) |
|||
|
|||
/* transmit data byte 3 */ |
|||
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) |
|||
|
|||
/* transmit data byte 4 */ |
|||
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) |
|||
|
|||
/* transmit data byte 5 */ |
|||
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) |
|||
|
|||
/* transmit data byte 6 */ |
|||
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) |
|||
|
|||
/* transmit data byte 7 */ |
|||
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) |
|||
|
|||
/* receive mailbox extended identifier*/ |
|||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) |
|||
|
|||
/* receive mailbox standrad identifier*/ |
|||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) |
|||
|
|||
/* receive data length */ |
|||
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) |
|||
|
|||
/* the index of the filter by which the frame is passed */ |
|||
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) |
|||
|
|||
/* receive data byte 0 */ |
|||
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) |
|||
|
|||
/* receive data byte 1 */ |
|||
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) |
|||
|
|||
/* receive data byte 2 */ |
|||
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) |
|||
|
|||
/* receive data byte 3 */ |
|||
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) |
|||
|
|||
/* receive data byte 4 */ |
|||
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) |
|||
|
|||
/* receive data byte 5 */ |
|||
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) |
|||
|
|||
/* receive data byte 6 */ |
|||
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) |
|||
|
|||
/* receive data byte 7 */ |
|||
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) |
|||
|
|||
/* error number */ |
|||
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) |
|||
|
|||
/* transmit error count */ |
|||
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) |
|||
|
|||
/* receive error count */ |
|||
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) |
|||
|
|||
/* CAN errors */ |
|||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) |
|||
#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ |
|||
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ |
|||
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ |
|||
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ |
|||
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ |
|||
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ |
|||
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ |
|||
#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ |
|||
|
|||
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ |
|||
|
|||
/* CAN communication mode */ |
|||
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ |
|||
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ |
|||
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ |
|||
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ |
|||
|
|||
/* CAN resynchronisation jump width */ |
|||
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ |
|||
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ |
|||
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ |
|||
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ |
|||
|
|||
/* CAN time segment 1 */ |
|||
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ |
|||
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ |
|||
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ |
|||
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ |
|||
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ |
|||
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ |
|||
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ |
|||
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ |
|||
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ |
|||
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ |
|||
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ |
|||
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ |
|||
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ |
|||
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ |
|||
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ |
|||
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ |
|||
|
|||
/* CAN time segment 2 */ |
|||
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ |
|||
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ |
|||
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ |
|||
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ |
|||
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ |
|||
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ |
|||
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ |
|||
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ |
|||
|
|||
/* CAN mailbox number */ |
|||
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ |
|||
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ |
|||
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ |
|||
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ |
|||
|
|||
/* CAN frame format */ |
|||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ |
|||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ |
|||
|
|||
/* CAN receive fifo */ |
|||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ |
|||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ |
|||
|
|||
/* frame number of receive fifo */ |
|||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ |
|||
|
|||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ |
|||
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ |
|||
|
|||
/* CAN working mode */ |
|||
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ |
|||
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ |
|||
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ |
|||
|
|||
/* filter bits */ |
|||
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ |
|||
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ |
|||
|
|||
/* filter mode */ |
|||
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ |
|||
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ |
|||
|
|||
/* filter 16 bits mask */ |
|||
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ |
|||
|
|||
/* frame type */ |
|||
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ |
|||
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ |
|||
|
|||
/* CAN timeout */ |
|||
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ |
|||
|
|||
/* interrupt enable bits */ |
|||
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ |
|||
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ |
|||
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ |
|||
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ |
|||
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ |
|||
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ |
|||
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ |
|||
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ |
|||
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ |
|||
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ |
|||
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ |
|||
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ |
|||
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ |
|||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ |
|||
|
|||
/* function declarations */ |
|||
/* deinitialize CAN */ |
|||
void can_deinit(uint32_t can_periph); |
|||
/* initialize CAN struct */ |
|||
void can_struct_para_init(can_struct_type_enum type, void* p_struct); |
|||
/* initialize CAN */ |
|||
ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); |
|||
/* CAN filter init */ |
|||
void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); |
|||
/* set can1 fliter start bank number */ |
|||
void can1_filter_start_bank(uint8_t start_bank); |
|||
/* enable functions */ |
|||
/* CAN debug freeze enable */ |
|||
void can_debug_freeze_enable(uint32_t can_periph); |
|||
/* CAN debug freeze disable */ |
|||
void can_debug_freeze_disable(uint32_t can_periph); |
|||
/* CAN time trigger mode enable */ |
|||
void can_time_trigger_mode_enable(uint32_t can_periph); |
|||
/* CAN time trigger mode disable */ |
|||
void can_time_trigger_mode_disable(uint32_t can_periph); |
|||
|
|||
/* transmit functions */ |
|||
/* transmit CAN message */ |
|||
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); |
|||
/* get CAN transmit state */ |
|||
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); |
|||
/* stop CAN transmission */ |
|||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); |
|||
/* CAN receive message */ |
|||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); |
|||
/* CAN release fifo */ |
|||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); |
|||
/* CAN receive message length */ |
|||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); |
|||
/* CAN working mode */ |
|||
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); |
|||
/* CAN wakeup from sleep mode */ |
|||
ErrStatus can_wakeup(uint32_t can_periph); |
|||
|
|||
/* CAN get error */ |
|||
can_error_enum can_error_get(uint32_t can_periph); |
|||
/* get CAN receive error number */ |
|||
uint8_t can_receive_error_number_get(uint32_t can_periph); |
|||
/* get CAN transmit error number */ |
|||
uint8_t can_transmit_error_number_get(uint32_t can_periph); |
|||
|
|||
/* CAN interrupt enable */ |
|||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); |
|||
/* CAN interrupt disable */ |
|||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); |
|||
/* CAN get flag state */ |
|||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); |
|||
/* CAN clear flag state */ |
|||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag); |
|||
/* CAN get interrupt flag state */ |
|||
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); |
|||
/* CAN clear interrupt flag state */ |
|||
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); |
|||
|
|||
#endif /* GD32VF103_CAN_H */ |
|||
@ -0,0 +1,78 @@ |
|||
/*!
|
|||
\file gd32vf103_crc.h |
|||
\brief definitions for the CRC |
|||
|
|||
|
|||
\version 2019-06-05, V1.0.0, firmware for GD32VF103 |
|||
*/ |
|||
|
|||
/*
|
|||
Copyright (c) 2019, GigaDevice Semiconductor Inc. |
|||
|
|||
Redistribution and use in source and binary forms, with or without modification, |
|||
are permitted provided that the following conditions are met: |
|||
|
|||
1. Redistributions of source code must retain the above copyright notice, this |
|||
list of conditions and the following disclaimer. |
|||
2. Redistributions in binary form must reproduce the above copyright notice, |
|||
this list of conditions and the following disclaimer in the documentation |
|||
and/or other materials provided with the distribution. |
|||
3. Neither the name of the copyright holder nor the names of its contributors |
|||
may be used to endorse or promote products derived from this software without |
|||
specific prior written permission. |
|||
|
|||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
|||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
|||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
|||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
|||
OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef GD32VF103_CRC_H |
|||
#define GD32VF103_CRC_H |
|||
|
|||
#include "gd32vf103.h" |
|||
|
|||
/* CRC definitions */ |
|||
#define CRC CRC_BASE |
|||
|
|||
/* registers definitions */ |
|||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ |
|||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ |
|||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ |
|||
|
|||
/* bits definitions */ |
|||
/* CRC_DATA */ |
|||
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ |
|||
|
|||
/* CRC_FDATA */ |
|||
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ |
|||
|
|||
/* CRC_CTL */ |
|||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ |
|||
|
|||
/* function declarations */ |
|||
/* deinit CRC calculation unit */ |
|||
void crc_deinit(void); |
|||
|
|||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ |
|||
void crc_data_register_reset(void); |
|||
/* read the value of the data register */ |
|||
uint32_t crc_data_register_read(void); |
|||
|
|||
/* read the value of the free data register */ |
|||
uint8_t crc_free_data_register_read(void); |
|||
/* write data to the free data register */ |
|||
void crc_free_data_register_write(uint8_t free_data); |
|||
|
|||
/* calculate the CRC value of a 32-bit data */ |
|||
uint32_t crc_single_data_calculate(uint32_t sdata); |
|||
/* calculate the CRC value of an array of 32-bit values */ |
|||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); |
|||
|
|||
#endif /* GD32VF103_CRC_H */ |
|||
@ -0,0 +1,242 @@ |
|||
/*!
|
|||
\file gd32vf103_dac.h |
|||
\brief definitions for the DAC |
|||
|
|||
\version 2019-06-05, V1.0.0, firmware for GD32VF103 |
|||
*/ |
|||
|
|||
/*
|
|||
Copyright (c) 2019, GigaDevice Semiconductor Inc. |
|||
|
|||
Redistribution and use in source and binary forms, with or without modification, |
|||
are permitted provided that the following conditions are met: |
|||
|
|||
1. Redistributions of source code must retain the above copyright notice, this |
|||
list of conditions and the following disclaimer. |
|||
2. Redistributions in binary form must reproduce the above copyright notice, |
|||
this list of conditions and the following disclaimer in the documentation |
|||
and/or other materials provided with the distribution. |
|||
3. Neither the name of the copyright holder nor the names of its contributors |
|||
may be used to endorse or promote products derived from this software without |
|||
specific prior written permission. |
|||
|
|||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
|||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
|||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
|||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
|||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
|||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
|||
OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef GD32VF103_DAC_H |
|||
#define GD32VF103_DAC_H |
|||
|
|||
#include "gd32vf103.h" |
|||
|
|||
/* DACx(x=0,1) definitions */ |
|||
#define DAC DAC_BASE |
|||
#define DAC0 (0U) |
|||
#define DAC1 (1U) |
|||
|
|||
/* registers definitions */ |
|||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ |
|||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ |
|||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ |
|||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ |
|||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ |
|||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ |
|||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ |
|||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ |
|||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ |
|||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ |
|||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ |
|||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ |
|||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ |
|||
|
|||
/* bits definitions */ |
|||
/* DAC_CTL */ |
|||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ |
|||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ |
|||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ |
|||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ |
|||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ |
|||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ |
|||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ |
|||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ |
|||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ |
|||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ |
|||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ |
|||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ |
|||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ |
|||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ |
|||
|
|||
/* DAC_SWT */ |
|||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ |
|||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ |
|||
|
|||
/* DAC0_R12DH */ |
|||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ |
|||
|
|||
/* DAC0_L12DH */ |
|||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ |
|||
|
|||
/* DAC0_R8DH */ |
|||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ |
|||
|
|||
/* DAC1_R12DH */ |
|||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ |
|||
|
|||
/* DAC1_L12DH */ |
|||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ |
|||
|
|||
/* DAC1_R8DH */ |
|||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ |
|||
|
|||
/* DACC_R12DH */ |
|||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ |
|||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ |
|||
|
|||
/* DACC_L12DH */ |
|||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ |
|||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ |
|||
|
|||
/* DACC_R8DH */ |
|||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ |
|||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ |
|||
|
|||
/* DAC0_DO */ |
|||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ |
|||
|
|||
/* DAC1_DO */ |
|||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ |
|||
|
|||
/* constants definitions */ |
|||
/* DAC trigger source */ |
|||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) |
|||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ |
|||
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ |
|||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ |
|||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ |
|||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ |
|||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ |
|||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ |
|||