@ -866,7 +866,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
}
}
else if ( ( hhcd - > hc [ chnum ] . state = = HC_XACTERR ) | |
else if ( ( hhcd - > hc [ chnum ] . state = = HC_XACTERR ) | |
( hhcd - > hc [ chnum ] . state = = HC_DATATGLERR ) )
( hhcd - > hc [ chnum ] . state = = HC_DATATGLERR ) | |
( hhcd - > hc [ chnum ] . state = = HC_NAK ) )
{
{
if ( hhcd - > hc [ chnum ] . ErrCnt + + > 3 )
if ( hhcd - > hc [ chnum ] . ErrCnt + + > 3 )
{
{
@ -899,20 +900,20 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
else if ( ( USBx_HC ( chnum ) - > HCINT ) & USB_OTG_HCINT_NAK )
else if ( ( USBx_HC ( chnum ) - > HCINT ) & USB_OTG_HCINT_NAK )
{
{
hhcd - > hc [ chnum ] . ErrCnt = 0 ;
hhcd - > hc [ chnum ] . ErrCnt = 0 ;
if ( hhcd - > hc [ chnum ] . ep_type = = EP_TYPE_INTR )
// if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
// {
__HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) ;
__HAL_HCD_UNMASK_HALT_HC_INT ( chnum ) ;
USB_HC_Halt ( hhcd - > Instance , chnum ) ;
USB_HC_Halt ( hhcd - > Instance , chnum ) ;
}
// }
else if ( ( hhcd - > hc [ chnum ] . ep_type = = EP_TYPE_CTRL ) | |
// else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
( hhcd - > hc [ chnum ] . ep_type = = EP_TYPE_BULK ) )
// (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
// {
/* re-activate the channel */
// /* re-activate the channel */
tmpreg = USBx_HC ( chnum ) - > HCCHAR ;
// tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg & = ~ USB_OTG_HCCHAR_CHDIS ;
// tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg | = USB_OTG_HCCHAR_CHENA ;
// tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC ( chnum ) - > HCCHAR = tmpreg ;
// USBx_HC(chnum)->HCCHAR = tmpreg;
}
// }
hhcd - > hc [ chnum ] . state = HC_NAK ;
hhcd - > hc [ chnum ] . state = HC_NAK ;
__HAL_HCD_CLEAR_HC_INT ( chnum , USB_OTG_HCINT_NAK ) ;
__HAL_HCD_CLEAR_HC_INT ( chnum , USB_OTG_HCINT_NAK ) ;
}
}
@ -1014,13 +1015,6 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
{
__HAL_HCD_MASK_HALT_HC_INT ( chnum ) ;
__HAL_HCD_MASK_HALT_HC_INT ( chnum ) ;
//This shouldn't even exist. So there's a weird host controller hardware bug
//on the STM32F407 that manifests when writing to some FAT filesystems.
//Transactions will stop partway through a 512-byte write, and nothing can
//get them started again. We can avoid this by soft-resetting the
//AHB-interface state machines on every channel halt.
USBx - > GRSTCTL | = USB_OTG_GRSTCTL_HSRST ;
if ( hhcd - > hc [ chnum ] . state = = HC_XFRC )
if ( hhcd - > hc [ chnum ] . state = = HC_XFRC )
{
{
hhcd - > hc [ chnum ] . urb_state = URB_DONE ;
hhcd - > hc [ chnum ] . urb_state = URB_DONE ;