Ivan Olenichev
6 years ago
parent
686b9289cf
commit
70c746113a
@ -0,0 +1,176 @@
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module i2c_slave (input CLK,
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input SCL, /*inout SDA,*/SDA_IN, output SDA_OUT, // FOR TEST
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output IS_TRANSMISSION, output IS_READ, output IS_ACK, output WR, //output ACK_MASTER_CTRL,
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output /*reg*/ [7:0] RECEIVED_BYTE, input [7:0] BYTE_TO_TRANSMIT,
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output [(MAX_I2C_TRANSACTION_EXP2-1):0] COUNTER);
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// ALL OPERATIONS WITH MEMORY ARE IN POSEDGE CLK, IN NEGEDGE - ONLY SCL AND SDA LATCH
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// COUNTER = 0 - ADRESS RECEIVED, COUNTER >=1 - DATA TRANSMISSION
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// RECEIVED BYTES MUST READ WHEN WR POSEDGE, ADRESS NOT READING ###AND BYTE COUNTER >=1 (BYTE COUNTER = 0 - ADRESS)
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// BYTES TO TRANSMIT MUST WRITE WHEN WR POSEDGE, BYTE COUNTER CAN BE ZERO
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// (FIRST BYTE TRANSMITTED AFTER ADRESS).
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// LAST BYTE HAS NO WR ####BUT LAST BYTE NOT TRANSMITTED (DECAUSE MASTER STOPS TRANSMIT)
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parameter I2C_ADRESS = 7'h34;
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parameter MAX_I2C_TRANSACTION_EXP2 = 9; // !!! - FOR LIMIT BYTES TO TX/RX (WITH ADRESS)
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reg /*SDA_IN,*/ SDA_DIR;//, SDA_OUT; // DELETED FOR TEST
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initial begin
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//SDA_OUT = 0; // DELETED FOR TEST
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SCLD = 1;
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SDAD = 1;
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end
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reg SCLD, SDAD;
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reg SCL_LAST, SDA_LAST;
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reg i2c_state_machine;
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initial begin
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SCL_LAST = 1; SDA_LAST = 1; i2c_state_machine = 0;
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end
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reg is_read;
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reg [3:0] i2c_bit_counter;
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reg [7:0] received_byte;
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reg [7:0] byte_to_transmit;
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reg [(MAX_I2C_TRANSACTION_EXP2-1):0] byte_counter;
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//reg is_for_me;
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reg is_ack;
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reg wr;//reg ack_master_ctrl;
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// FILTER
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reg SCLF, SDAF;
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reg [3:0] scl_cnt, sda_cnt;
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always@(negedge CLK) begin
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SCLF = SCL;
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SDAF = SDA_IN;
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end
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always@(posedge CLK) begin
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if (scl_cnt != 0) begin
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scl_cnt = scl_cnt - 1;
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if (scl_cnt == 0) begin
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if (SCLD != SCLF)
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SCLD = SCLF;
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end
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end
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else begin
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if (SCLD != SCLF)
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scl_cnt = 3'd7;
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end
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if (sda_cnt != 0) begin
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sda_cnt = sda_cnt - 1;
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if (sda_cnt == 0) begin
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if (SDAD != SDAF)
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SDAD = SDAF;
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end
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end
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else begin
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if (SDAD != SDAF)
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sda_cnt = 3'd7;
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end
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// END OF FILTER
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//SDA_IN = SDA; // FOR IVERILOG
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if ((SDAD == 0) && (SDA_LAST == 1) && (SCLD == 1)) begin
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i2c_state_machine = 1;
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i2c_bit_counter = 4'd8;
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byte_counter = 9'd0;
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is_read = 0;
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//is_for_me = 1; // RESETS TO ZERO WHEN ADRESS CHECKING
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SDA_DIR = 0;
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is_ack = 0;
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//ack_master_ctrl = 1;
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wr = 0;
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end
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if ((SDAD == 1) && (SDA_LAST == 0) && (SCLD == 1)) begin
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i2c_state_machine = 0;
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SDA_DIR = 0;
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wr = 0;
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end
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if (i2c_state_machine/* && is_for_me*/) begin
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if (!is_read) begin
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if (i2c_bit_counter > 0) begin
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if ((SCL_LAST == 0) && (SCLD == 1)) begin
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received_byte[i2c_bit_counter-1] = SDAD;
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i2c_bit_counter = i2c_bit_counter - 1;
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end
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end
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else begin
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if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin
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if (byte_counter == 0) begin
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if (received_byte[7:1] != I2C_ADRESS)
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i2c_state_machine = 0; //is_for_me = 0;
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is_read = received_byte[0];
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end
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else begin
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// EMIT SIGNAL OF BYTE RECEIVING
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end
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if (byte_counter != (2^MAX_I2C_TRANSACTION_EXP2 - 1))
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byte_counter = byte_counter + 1;
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SDA_DIR = i2c_state_machine; //is_for_me;
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is_ack = i2c_state_machine; //1;
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//if (is_read) begin
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// i2c_bit_counter = 8;
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//end
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end
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else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1) && (byte_counter > 1))
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wr = 1;
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else if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 1)) begin
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is_ack = 0;
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SDA_DIR = 0;
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i2c_bit_counter = 4'd8;
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wr = 0;
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end
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end
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end
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else begin // IS_READ
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if (i2c_bit_counter > 0) begin
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if ((SCL_LAST == 1) && (SCLD == 0)) begin
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wr = 0;
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SDA_DIR = (BYTE_TO_TRANSMIT[i2c_bit_counter-1] ^ 1) /*& is_for_me & ack_master_ctrl*/;
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i2c_bit_counter = i2c_bit_counter - 1;
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is_ack = 0;
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end
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end
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else begin
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if ((SCL_LAST == 1) && (SCLD == 0) && (is_ack == 0)) begin
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SDA_DIR = 0;
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is_ack = 1;
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end
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else if ((SCL_LAST == 0) && (SCLD == 1) && (is_ack == 1)) begin
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i2c_bit_counter = 8;
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i2c_state_machine = (SDAD ^ 1) | SDA_DIR; //ack_master_ctrl = SDAD+1; // MAYBE TRANSMIT BYTE REPEAT
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wr = (SDAD ^ 1) | SDA_DIR;
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if (byte_counter != (2^MAX_I2C_TRANSACTION_EXP2 - 1))
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byte_counter = byte_counter + 1;
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// EMIT SIGNAL OF BYTE TO TRANSMIT
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end
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end
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end
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end
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SCL_LAST <= SCLD;
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SDA_LAST <= SDAD;
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//SDA_OUT = (SDA_DIR ^ 1) & SDA; // FOR IVERILOG
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end
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assign IS_TRANSMISSION = i2c_state_machine;
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//assign SDA = SDA_DIR ? 1'b0 : 1'bz;
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assign IS_ACK = is_ack;
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assign IS_READ = is_read;
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assign WR = wr;//assign ACK_MASTER_CTRL = ack_master_ctrl;
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assign RECEIVED_BYTE = received_byte;
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//assign BYTE_TO_TRANSMIT = byte_to_transmit;
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assign COUNTER = byte_counter;
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assign SDA_OUT = SDA_DIR ^ 1;
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/* SB_IO #(
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.PIN_TYPE(6'b 1010_01),
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.PULLUP(1'b 0)
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) led_io (
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.PACKAGE_PIN(SDA),
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.OUTPUT_ENABLE(SDA_DIR),
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.D_OUT_0(SDA_OUT),
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.D_IN_0(SDA_IN)
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); */ // DELETED FOR TEST
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endmodule
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,631 @@
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#! /usr/local/bin/vvp
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:ivl_version "10.1 (stable)" "(v10_1-109-g5474f9d)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "system";
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:vpi_module "vhdl_sys";
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:vpi_module "v2005_math";
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:vpi_module "va_math";
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S_0x14ddf70 .scope module, "test_counter" "test_counter" 2 1;
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.timescale 0 0;
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P_0x14e9670 .param/l "SCL_H" 0 2 44, +C4<00000000000000000000000001100100>;
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P_0x14e96b0 .param/l "SCL_L1" 0 2 45, +C4<00000000000000000000000001000110>;
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P_0x14e96f0 .param/l "SCL_L2" 0 2 46, +C4<00000000000000000000000000011110>;
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P_0x14e9730 .param/l "SDA_STT" 0 2 43, +C4<00000000000000000000000000011110>;
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L_0x152ac00 .functor BUFZ 8, v0x152a370_0, C4<00000000>, C4<00000000>, C4<00000000>;
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v0x1529820_0 .net "ACK", 0 0, L_0x152a480; 1 drivers
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v0x15298e0_0 .net "I2C_ACTIVITY", 0 0, L_0x152a410; 1 drivers
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v0x15299b0_0 .net "I2C_READ", 0 0, L_0x152a540; 1 drivers
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v0x1529ab0_0 .var "SCL", 0 0;
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v0x1529b80_0 .var "SDA", 0 0;
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v0x1529c20_0 .net "SDA_OUT", 0 0, L_0x152aac0; 1 drivers
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v0x1529cf0_0 .net "WR", 0 0, L_0x152a600; 1 drivers
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v0x1529dc0_0 .net "byte_to_transmit", 7 0, L_0x152ac00; 1 drivers
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v0x1529e90_0 .var "clk", 0 0;
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v0x1529ff0 .array "data_to", 0 4, 8 0;
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v0x152a090_0 .var "i", 8 0;
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v0x152a130_0 .net "i2c_counter", 8 0, L_0x152a7b0; 1 drivers
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v0x152a200_0 .var "j", 8 0;
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v0x152a2a0_0 .net "received_byte", 7 0, L_0x152a6f0; 1 drivers
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v0x152a370_0 .var "to_tx", 7 0;
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S_0x14ddb90 .scope module, "i2c" "i2c_slave" 2 15, 3 1 0, S_0x14ddf70;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "CLK"
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.port_info 1 /INPUT 1 "SCL"
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.port_info 2 /INPUT 1 "SDA_IN"
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.port_info 3 /OUTPUT 1 "SDA_OUT"
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.port_info 4 /OUTPUT 1 "IS_TRANSMISSION"
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.port_info 5 /OUTPUT 1 "IS_READ"
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.port_info 6 /OUTPUT 1 "IS_ACK"
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.port_info 7 /OUTPUT 1 "WR"
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.port_info 8 /OUTPUT 8 "RECEIVED_BYTE"
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.port_info 9 /INPUT 8 "BYTE_TO_TRANSMIT"
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.port_info 10 /OUTPUT 9 "COUNTER"
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P_0x1503870 .param/l "I2C_ADRESS" 0 3 13, C4<0110100>;
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P_0x15038b0 .param/l "MAX_I2C_TRANSACTION_EXP2" 0 3 14, +C4<00000000000000000000000000001001>;
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L_0x152a410 .functor BUFZ 1, v0x15290c0_0, C4<0>, C4<0>, C4<0>;
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L_0x152a480 .functor BUFZ 1, v0x1529180_0, C4<0>, C4<0>, C4<0>;
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L_0x152a540 .functor BUFZ 1, v0x1529240_0, C4<0>, C4<0>, C4<0>;
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L_0x152a600 .functor BUFZ 1, v0x15295a0_0, C4<0>, C4<0>, C4<0>;
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L_0x152a6f0 .functor BUFZ 8, v0x1529300_0, C4<00000000>, C4<00000000>, C4<00000000>;
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L_0x152a7b0 .functor BUFZ 9, v0x1528f00_0, C4<000000000>, C4<000000000>, C4<000000000>;
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L_0x7faeab837060 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
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L_0x152a980 .functor XOR 2, L_0x152a8b0, L_0x7faeab837060, C4<00>, C4<00>;
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v0x14de350_0 .net "BYTE_TO_TRANSMIT", 7 0, L_0x152ac00; alias, 1 drivers
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v0x1527d00_0 .net "CLK", 0 0, v0x1529e90_0; 1 drivers
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v0x1527dc0_0 .net "COUNTER", 8 0, L_0x152a7b0; alias, 1 drivers
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v0x1527eb0_0 .net "IS_ACK", 0 0, L_0x152a480; alias, 1 drivers
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v0x1527f70_0 .net "IS_READ", 0 0, L_0x152a540; alias, 1 drivers
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v0x1528080_0 .net "IS_TRANSMISSION", 0 0, L_0x152a410; alias, 1 drivers
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v0x1528140_0 .net "RECEIVED_BYTE", 7 0, L_0x152a6f0; alias, 1 drivers
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v0x1528220_0 .net "SCL", 0 0, v0x1529ab0_0; 1 drivers
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v0x15282e0_0 .var "SCLD", 0 0;
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v0x1528430_0 .var "SCLF", 0 0;
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v0x15284f0_0 .var "SCL_LAST", 0 0;
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v0x15285b0_0 .var "SDAD", 0 0;
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v0x1528670_0 .var "SDAF", 0 0;
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v0x1528730_0 .var "SDA_DIR", 0 0;
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v0x15287f0_0 .net "SDA_IN", 0 0, v0x1529b80_0; 1 drivers
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v0x15288b0_0 .var "SDA_LAST", 0 0;
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v0x1528970_0 .net "SDA_OUT", 0 0, L_0x152aac0; alias, 1 drivers
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v0x1528b20_0 .net "WR", 0 0, L_0x152a600; alias, 1 drivers
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v0x1528bc0_0 .net *"_s12", 1 0, L_0x152a8b0; 1 drivers
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L_0x7faeab837018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
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v0x1528c60_0 .net *"_s15", 0 0, L_0x7faeab837018; 1 drivers
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v0x1528d40_0 .net/2u *"_s16", 1 0, L_0x7faeab837060; 1 drivers
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v0x1528e20_0 .net *"_s18", 1 0, L_0x152a980; 1 drivers
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v0x1528f00_0 .var "byte_counter", 8 0;
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v0x1528fe0_0 .var "i2c_bit_counter", 3 0;
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v0x15290c0_0 .var "i2c_state_machine", 0 0;
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v0x1529180_0 .var "is_ack", 0 0;
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v0x1529240_0 .var "is_read", 0 0;
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v0x1529300_0 .var "received_byte", 7 0;
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v0x15293e0_0 .var "scl_cnt", 3 0;
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v0x15294c0_0 .var "sda_cnt", 3 0;
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v0x15295a0_0 .var "wr", 0 0;
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E_0x14ddd50 .event posedge, v0x1527d00_0;
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E_0x14dd970 .event negedge, v0x1527d00_0;
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L_0x152a8b0 .concat [ 1 1 0 0], v0x1528730_0, L_0x7faeab837018;
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L_0x152aac0 .part L_0x152a980, 0, 1;
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.scope S_0x14ddb90;
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T_0 ;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x15282e0_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x15285b0_0, 0, 1;
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%end;
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.thread T_0;
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.scope S_0x14ddb90;
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T_1 ;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x15284f0_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x15288b0_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x15290c0_0, 0, 1;
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%end;
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.thread T_1;
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.scope S_0x14ddb90;
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T_2 ;
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%wait E_0x14dd970;
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%load/vec4 v0x1528220_0;
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%store/vec4 v0x1528430_0, 0, 1;
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%load/vec4 v0x15287f0_0;
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%store/vec4 v0x1528670_0, 0, 1;
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%jmp T_2;
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.thread T_2;
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.scope S_0x14ddb90;
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T_3 ;
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%wait E_0x14ddd50;
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%load/vec4 v0x15293e0_0;
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%pad/u 32;
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%cmpi/ne 0, 0, 32;
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%jmp/0xz T_3.0, 4;
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%load/vec4 v0x15293e0_0;
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%subi 1, 0, 4;
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%store/vec4 v0x15293e0_0, 0, 4;
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%load/vec4 v0x15293e0_0;
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%pad/u 32;
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%cmpi/e 0, 0, 32;
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%jmp/0xz T_3.2, 4;
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%load/vec4 v0x15282e0_0;
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%load/vec4 v0x1528430_0;
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%cmp/ne;
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%jmp/0xz T_3.4, 4;
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%load/vec4 v0x1528430_0;
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%store/vec4 v0x15282e0_0, 0, 1;
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T_3.4 ;
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T_3.2 ;
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%jmp T_3.1;
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T_3.0 ;
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%load/vec4 v0x15282e0_0;
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%load/vec4 v0x1528430_0;
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%cmp/ne;
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%jmp/0xz T_3.6, 4;
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%pushi/vec4 7, 0, 4;
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%store/vec4 v0x15293e0_0, 0, 4;
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T_3.6 ;
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T_3.1 ;
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%load/vec4 v0x15294c0_0;
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%pad/u 32;
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%cmpi/ne 0, 0, 32;
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%jmp/0xz T_3.8, 4;
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%load/vec4 v0x15294c0_0;
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%subi 1, 0, 4;
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%store/vec4 v0x15294c0_0, 0, 4;
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%load/vec4 v0x15294c0_0;
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%pad/u 32;
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%cmpi/e 0, 0, 32;
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%jmp/0xz T_3.10, 4;
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%load/vec4 v0x15285b0_0;
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%load/vec4 v0x1528670_0;
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%cmp/ne;
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%jmp/0xz T_3.12, 4;
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%load/vec4 v0x1528670_0;
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%store/vec4 v0x15285b0_0, 0, 1;
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T_3.12 ;
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T_3.10 ;
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%jmp T_3.9;
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T_3.8 ;
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%load/vec4 v0x15285b0_0;
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%load/vec4 v0x1528670_0;
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%cmp/ne;
|
||||
%jmp/0xz T_3.14, 4;
|
||||
%pushi/vec4 7, 0, 4;
|
||||
%store/vec4 v0x15294c0_0, 0, 4;
|
||||
T_3.14 ;
|
||||
T_3.9 ;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15288b0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.16, 8;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x15290c0_0, 0, 1;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x1528fe0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%store/vec4 v0x1528f00_0, 0, 9;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529240_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529180_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
T_3.16 ;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15288b0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.18, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15290c0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
T_3.18 ;
|
||||
%load/vec4 v0x15290c0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.20, 8;
|
||||
%load/vec4 v0x1529240_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.22, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%pad/u 32;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_3.24, 5;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.26, 8;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%pad/u 32;
|
||||
%subi 1, 0, 32;
|
||||
%ix/vec4 4;
|
||||
%store/vec4 v0x1529300_0, 4, 1;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%subi 1, 0, 4;
|
||||
%store/vec4 v0x1528fe0_0, 0, 4;
|
||||
T_3.26 ;
|
||||
%jmp T_3.25;
|
||||
T_3.24 ;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x1529180_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.28, 8;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 0, 0, 32;
|
||||
%jmp/0xz T_3.30, 4;
|
||||
%load/vec4 v0x1529300_0;
|
||||
%parti/s 7, 1, 2;
|
||||
%cmpi/ne 52, 0, 7;
|
||||
%jmp/0xz T_3.32, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15290c0_0, 0, 1;
|
||||
T_3.32 ;
|
||||
%load/vec4 v0x1529300_0;
|
||||
%parti/s 1, 0, 2;
|
||||
%store/vec4 v0x1529240_0, 0, 1;
|
||||
T_3.30 ;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%pad/u 32;
|
||||
%cmpi/ne 10, 0, 32;
|
||||
%jmp/0xz T_3.34, 4;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%addi 1, 0, 9;
|
||||
%store/vec4 v0x1528f00_0, 0, 9;
|
||||
T_3.34 ;
|
||||
%load/vec4 v0x15290c0_0;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%load/vec4 v0x15290c0_0;
|
||||
%store/vec4 v0x1529180_0, 0, 1;
|
||||
%jmp T_3.29;
|
||||
T_3.28 ;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x1529180_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%pad/u 32;
|
||||
%cmp/u;
|
||||
%flag_get/vec4 5;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.36, 8;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
%jmp T_3.37;
|
||||
T_3.36 ;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x1529180_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.38, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529180_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x1528fe0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
T_3.38 ;
|
||||
T_3.37 ;
|
||||
T_3.29 ;
|
||||
T_3.25 ;
|
||||
%jmp T_3.23;
|
||||
T_3.22 ;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%pad/u 32;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_3.40, 5;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.42, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
%load/vec4 v0x14de350_0;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%pad/u 32;
|
||||
%subi 1, 0, 32;
|
||||
%part/u 1;
|
||||
%pad/u 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%xor;
|
||||
%pad/u 1;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%load/vec4 v0x1528fe0_0;
|
||||
%subi 1, 0, 4;
|
||||
%store/vec4 v0x1528fe0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529180_0, 0, 1;
|
||||
T_3.42 ;
|
||||
%jmp T_3.41;
|
||||
T_3.40 ;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x1529180_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.44, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1528730_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529180_0, 0, 1;
|
||||
%jmp T_3.45;
|
||||
T_3.44 ;
|
||||
%load/vec4 v0x15284f0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%load/vec4 v0x1529180_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.46, 8;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x1528fe0_0, 0, 4;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%pad/u 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%xor;
|
||||
%load/vec4 v0x1528730_0;
|
||||
%pad/u 2;
|
||||
%or;
|
||||
%pad/u 1;
|
||||
%store/vec4 v0x15290c0_0, 0, 1;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%pad/u 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%xor;
|
||||
%load/vec4 v0x1528730_0;
|
||||
%pad/u 2;
|
||||
%or;
|
||||
%pad/u 1;
|
||||
%store/vec4 v0x15295a0_0, 0, 1;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%pad/u 32;
|
||||
%cmpi/ne 10, 0, 32;
|
||||
%jmp/0xz T_3.48, 4;
|
||||
%load/vec4 v0x1528f00_0;
|
||||
%addi 1, 0, 9;
|
||||
%store/vec4 v0x1528f00_0, 0, 9;
|
||||
T_3.48 ;
|
||||
T_3.46 ;
|
||||
T_3.45 ;
|
||||
T_3.41 ;
|
||||
T_3.23 ;
|
||||
T_3.20 ;
|
||||
%load/vec4 v0x15282e0_0;
|
||||
%assign/vec4 v0x15284f0_0, 0;
|
||||
%load/vec4 v0x15285b0_0;
|
||||
%assign/vec4 v0x15288b0_0, 0;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
.scope S_0x14ddf70;
|
||||
T_4 ;
|
||||
%pushi/vec4 197, 0, 8;
|
||||
%store/vec4 v0x152a370_0, 0, 8;
|
||||
%end;
|
||||
.thread T_4;
|
||||
.scope S_0x14ddf70;
|
||||
T_5 ;
|
||||
%delay 1, 0;
|
||||
%load/vec4 v0x1529e90_0;
|
||||
%inv;
|
||||
%store/vec4 v0x1529e90_0, 0, 1;
|
||||
%pushi/vec4 208, 0, 9;
|
||||
%ix/load 4, 0, 0;
|
||||
%flag_set/imm 4, 0;
|
||||
%store/vec4a v0x1529ff0, 4, 0;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%ix/load 4, 1, 0;
|
||||
%flag_set/imm 4, 0;
|
||||
%store/vec4a v0x1529ff0, 4, 0;
|
||||
%pushi/vec4 70, 0, 9;
|
||||
%ix/load 4, 2, 0;
|
||||
%flag_set/imm 4, 0;
|
||||
%store/vec4a v0x1529ff0, 4, 0;
|
||||
%pushi/vec4 16, 0, 9;
|
||||
%ix/load 4, 3, 0;
|
||||
%flag_set/imm 4, 0;
|
||||
%store/vec4a v0x1529ff0, 4, 0;
|
||||
%pushi/vec4 152, 0, 9;
|
||||
%ix/load 4, 4, 0;
|
||||
%flag_set/imm 4, 0;
|
||||
%store/vec4a v0x1529ff0, 4, 0;
|
||||
%jmp T_5;
|
||||
.thread T_5;
|
||||
.scope S_0x14ddf70;
|
||||
T_6 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529e90_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529ab0_0, 0, 1;
|
||||
%pushi/vec4 197, 0, 8;
|
||||
%store/vec4 v0x152a370_0, 0, 8;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529b80_0, 0, 1;
|
||||
%delay 500, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529b80_0, 0, 1;
|
||||
%delay 30, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529ab0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%store/vec4 v0x152a090_0, 0, 9;
|
||||
T_6.0 ;
|
||||
%load/vec4 v0x152a090_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 5, 0, 32;
|
||||
%jmp/0xz T_6.1, 5;
|
||||
%delay 200, 0;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%store/vec4 v0x152a200_0, 0, 9;
|
||||
T_6.2 ;
|
||||
%load/vec4 v0x152a200_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 9, 0, 32;
|
||||
%jmp/0xz T_6.3, 5;
|
||||
%delay 70, 0;
|
||||
%ix/getv 4, v0x152a090_0;
|
||||
%load/vec4a v0x1529ff0, 4;
|
||||
%pushi/vec4 8, 0, 32;
|
||||
%load/vec4 v0x152a200_0;
|
||||
%pad/u 32;
|
||||
%sub;
|
||||
%part/u 1;
|
||||
%store/vec4 v0x1529b80_0, 0, 1;
|
||||
%delay 30, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529ab0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529ab0_0, 0, 1;
|
||||
%load/vec4 v0x152a200_0;
|
||||
%pushi/vec4 1, 0, 9;
|
||||
%add;
|
||||
%store/vec4 v0x152a200_0, 0, 9;
|
||||
%jmp T_6.2;
|
||||
T_6.3 ;
|
||||
%load/vec4 v0x152a090_0;
|
||||
%pushi/vec4 1, 0, 9;
|
||||
%add;
|
||||
%store/vec4 v0x152a090_0, 0, 9;
|
||||
%jmp T_6.0;
|
||||
T_6.1 ;
|
||||
%delay 200, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x1529b80_0, 0, 1;
|
||||
%delay 200, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529ab0_0, 0, 1;
|
||||
%delay 40, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x1529b80_0, 0, 1;
|
||||
%end;
|
||||
.thread T_6;
|
||||
.scope S_0x14ddf70;
|
||||
T_7 ;
|
||||
%delay 11500, 0;
|
||||
%vpi_call 2 141 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_7;
|
||||
.scope S_0x14ddf70;
|
||||
T_8 ;
|
||||
%vpi_call 2 147 "$dumpfile", "out.vcd" {0 0 0};
|
||||
%vpi_call 2 148 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x14ddf70 {0 0 0};
|
||||
%end;
|
||||
.thread T_8;
|
||||
.scope S_0x14ddf70;
|
||||
T_9 ;
|
||||
%vpi_call 2 153 "$monitor", $stime, " ", v0x1529e90_0, " ", " ", v0x1529ab0_0, " ", v0x1529b80_0, " ", v0x15298e0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_9;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"test_i2c_slave.v";
|
||||
"i2c_slave.v";
|
||||
@ -0,0 +1,8 @@
|
||||
For simulation type command like:
|
||||
iverilog -o qqq i2c_slave.v test_i2c_slave_tx.v // FOR TX TO SLAVE
|
||||
iverilog -o qqq i2c_slave.v test_i2c_slave_rx.v // FOR RX FROM SLAVE
|
||||
|
||||
Then type command:
|
||||
vvp qqq
|
||||
|
||||
And open out.vcd with gtkwave
|
||||
Loading…
Reference in new issue