verilog no longer there

scripts/forksand-trellis-all

@@ -339,9 +339,9 @@ git submodule update &&							\
 #sed -i -e 's/main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now/main_ram_size = min(main_ram_size, 0x30000000) # FIXME: limit to 768MB for now/g' $FPGADIR/litex/litex/litex/soc/integration/soc_sdram.py && \
 #sed -i -e 's///g' $FPGADIR/litex/litex/litex/soc/integration/soc_core.py
 # BUILD VexRiscv.v HERE XXX
-cd litex/soc/cores/cpu/vexriscv/verilog && 				\
+#cd litex/soc/cores/cpu/vexriscv/verilog && 				\
 # Remove older builds
-rm -f *.v &&								\
+#rm -f *.v &&								\
 # BUILD VEXRISCV
 # 1m8s:
 make &&									\