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Code Issues 34 Pull Requests Releases Wiki Activity

hardware/mainboard: Connect DDR3 IO to FPGA IO

Browse Source 
Signed-off-by: David Shah <dave@ds0.me>
master
David Shah 6 years ago
parent 5b3022a492
commit 0d90bf76c4
9 changed files with 785 additions and 31 deletions
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2
hardware/ecp5_mainboard/ddr3.sch
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2
hardware/ecp5_mainboard/debug.sch
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8
hardware/ecp5_mainboard/ecp5_mainboard.sch
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hardware/ecp5_mainboard/fpga_io.sch
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U 1 1 61FB5AD2
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F 0 "#PWR?" H 3000 4050 50 0001 C CNN
F 1 "+1V35" H 3015 4373 50 0000 C CNN
F 2 "" H 3000 4200 50 0001 C CNN
F 3 "" H 3000 4200 50 0001 C CNN
1 3000 4200
1 0 0 -1
$EndComp
$Comp
L power:+1V35 #PWR?
U 1 1 61FB5BB5
P 5100 4200
F 0 "#PWR?" H 5100 4050 50 0001 C CNN
F 1 "+1V35" H 5115 4373 50 0000 C CNN
F 2 "" H 5100 4200 50 0001 C CNN
F 3 "" H 5100 4200 50 0001 C CNN
1 5100 4200
1 0 0 -1
$EndComp
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hardware/ecp5_mainboard/ports.sch
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hardware/ecp5_mainboard/power.sch
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hardware/ecp5_mainboard/serdes.sch
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