hardware/mainboard: Connect DDR3 IO to FPGA IO

Signed-off-by: David Shah <dave@ds0.me>
master
David Shah 6 years ago
parent 5b3022a492
commit 0d90bf76c4

@ -4,7 +4,7 @@ EELAYER 26 0
EELAYER END EELAYER END
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@ -56,4 +56,10 @@ U 6162FA9E
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$EndSCHEMATC $EndSCHEMATC

@ -0,0 +1,748 @@
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LIBS:ecp5_mainboard-cache
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DDR3_DQ17
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DDR3_DQ18
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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@ -4,7 +4,7 @@ EELAYER 26 0
EELAYER END EELAYER END
$Descr A3 16535 11693 $Descr A3 16535 11693
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Sheet 6 8 Sheet 6 9
Title "" Title ""
Date "" Date ""
Rev "" Rev ""

@ -4,7 +4,7 @@ EELAYER 26 0
EELAYER END EELAYER END
$Descr A3 16535 11693 $Descr A3 16535 11693
encoding utf-8 encoding utf-8
Sheet 2 8 Sheet 2 9
Title "" Title ""
Date "" Date ""
Rev "" Rev ""

@ -4,7 +4,7 @@ EELAYER 26 0
EELAYER END EELAYER END
$Descr A3 16535 11693 $Descr A3 16535 11693
encoding utf-8 encoding utf-8
Sheet 5 8 Sheet 5 9
Title "" Title ""
Date "" Date ""
Rev "" Rev ""

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