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@ -17,6 +17,7 @@ module led_ctrl (
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always @(posedge clk) ctr <= ctr + 1'b1;
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always @(posedge clk) ctr <= ctr + 1'b1;
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genvar i;
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genvar i;
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wire [11:0] led_o, led_en;
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generate
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generate
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for (i = 0; i < 12; i = i + 1'b1) begin
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for (i = 0; i < 12; i = i + 1'b1) begin
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/*
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/*
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@ -25,9 +26,11 @@ module led_ctrl (
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Only BG asserted : LED at constant 1'b1
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Only BG asserted : LED at constant 1'b1
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Neither asserted : LED off (1'bz)
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Neither asserted : LED off (1'bz)
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*/
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*/
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assign led_pin[i] = led_in_yr ?
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assign led_o[i] = led_in_yr[i] ?
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(led_in_bg ? ctr[DIV_FACTOR - 1] : 1'b0) :
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(led_in_bg[i] ? ctr[DIV_FACTOR - 1] : 1'b0) :
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(led_in_bg ? 1'b1 : 1'bz);
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1'b1;
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assign led_en[i] = led_in_yr[i] || led_in_bg[i];
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assign led_pin[i] = led_en[i] ? led_o[i] : 1'bz;
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end
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end
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endgenerate
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endgenerate
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