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# ULX3S PCB
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This is work-in-progress place for putting
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some wishes of a small (94x51 mm) FPGA board.
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Instead of describing in written,
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it is better explained when drawn in kicad:
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kicad ulx3s.pro
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[Schematics](/doc/schematics.pdf) is mostly complete.
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PCB routing is complete, but needs improvement
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mainly for the power supply.
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3D preview
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# Features
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FPGA: Lattice ECP5 LFE5U-25F-6BG381C
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USB: FTDI FT231XS (1Mbit JTAG and 3Mbit usbserial)
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GPIO: All differential, PMOD-friendly
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RAM: 32MB SDRAM MT48LC16M16
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Flash: 8MB SPI flash S25FL164 for FPGA config
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Storage: Micro-SD slot
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LEDs: 10 (8 blink-LEDs, 2 USB leds)
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Buttons: 6 (4 direction and 2 fire buttons)
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Audio: 3.5 mm stereo jack
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Video: GPDI connector with 3.3V-5V I2C bidirectional level shifter
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Display: placeholder for 0.96-1.3" SPI OLED COLOR or B/W
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WiFi+bluetooth: placeholder for ESP-32 (JTAG and serial over WiFi possible)
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Power: 3 Switching voltage regulators: 1.2V, 2.5V, 3.3V
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Low power sleep: RTC clock wakeup, quartz and battery
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GPDI is General Purpose Differential Interface,
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Electrically LVDS, mostly TMDS tolerant
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female receptacle more-or-less compatible
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with digital monitors/TVs
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# Todo
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Finish routing and especially improve Power
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section (thicker power lines, separately routed feedback)
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2.54 mm external JTAG header
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[x] Resistors for LEDs
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[x] Move USB LEDs from bottom to top side
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[ ] Improve SDRAM routing - use VIAs for closest pins
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[x] Increase thickness of power lines (5V, 3.3V, 2.5V)
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[x] Compile a f32c bitstream using the schematics
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[ ] Compile differential GPDI output
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[ ] Connect more lines from ESP-32 to FPGA
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[ ] Connect FPGA USB D+/D- with 1.5k pullup in USB 1.1 (full speed) mode
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[ ] Jumpers to switch 2.5V/3.3V for left IO banks
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[x] External JTAG header
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[ ] Move WiFi Disable jumper above the buttons
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[ ] Sprinkle 100nF capacitors on power lines
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[ ] Spice simulation of power-up/shutdown network
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[ ] Pin assignments wrong? Check schematic symbol pin names and
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pin-bank report project/project_project.dir/5_1.pad
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