Merge branch 'master' of https://github.com/emard/ulx3s

doc/MANUAL.md

@@ -124,7 +124,7 @@ Switching regulators use ferrite core coils L1,L2,L3 which can saturate
 at magnetic fields above 0.3T. Never approach neodymium magnets
 near powered board.
 
-# Programming over USB
+# Programming over USB port "US1"
 
 Use ftx_prog to allow max USB power consumption of 500mA
 and change product/manufacturer name of FT231X chip:
@@ -202,6 +202,48 @@ ${CHIP_ID} and ${FILE_SVF}:
     svf -tap lfe5.tap -quiet -progress ${FILE_SVF}
     shutdown
 
+# Programming over USB port "US2"
+
+There is possibility to program ULX3S SPI config FLASH thru
+US2 connector and
+a [fork of tinyfpga bootloader](https://github.com/tinyfpga/TinyFPGA-Bootloader) loaded
+to FPGA, either loaded from US1 temporary to FPGA SRAM or permanently 
+to SPI config FLASH. Bootloader uses multiboot feature of ECP5 FPGA.
+This programming option is experimental and not recommended for
+regular use.
+
+ULX3S with fully functional US2 bootloader can be used to program
+FPGA config FLASH without use of USB-serial chip FT231X.
+
+For bootloader convenience, it is recommended to solder D28 diode
+at empty placeholder located on back side near OLED and JTAG header.
+Observe diode polarity, see how other similar diodes are soldered on ULX3S.
+Any general purpose or schottky diode in SOD-323 package will fit
+like 1N914 1N4148 BAT54W etc. This diode will convert BTN0 function
+to unconditionally switch to next multiboot image by pulling down
+FPGA PROGRAMN pin.
+
+USB bootloader is in hacky state of development, you need hi quality
+USB cable, a compatible PC and selected USB port and too much luck (try
+all). I think bootloader's USB bus error recovery handling is wrong
+but sometimes it just works.
+US2 port should enumerate as some vendor specific USB-HID USB device
+and "tinyfpgasp" application can be used to write or read arbitrary
+image to FPGA SPI config FLASH.
+
+User bitstream should be uploaded to byte address 0x200000 of SPI config
+FLASH at 12/25/45F (I'm not sure for 85F).
+Bootloader in multiboot mode resides in multiple copies on SPI config
+FLASH chip. "primary"
+bootloader image is at byte address 0 of SPI config FLASH, "golden"
+bootloader image is at 0x140000 address on 45F chip but its location
+varies on various sizes of FPGA 12/25/45/85F. At the last 256 bytes of
+FLASH are some special FPGA lattice boot state machine commands
+(detailed meaning and format not yet known, it's like some primitive CPU
+assembly) that setups and controls multiboot function.
+Try not to overwrite any of boot related areas with something
+else otherwise US1 or JTAG recovery will be required.
+
 # Programming over JTAG header
 
 Any openocd compatible JTAG like FT2232 can be connected to JTAG header