schematics: v1.7.14

6 years ago · 32bd7673a8
parent 4890768c9c
commit 32bd7673a8
2 changed files with 5 additions and 5 deletions
--- a/ulx3s.sch
+++ b/ulx3s.sch
@ -49,7 +49,7 @@ encoding utf-8
 Sheet 1 11
 Title "ULX3S"
 Date ""
-Rev "1.7.12"
+Rev "1.7.14"
 Comp "FER+RIZ+RADIONA"
 Comment1 "Root sheet"
 Comment2 ""
--- a/usb.bak
+++ b/usb.bak
@ -754,10 +754,6 @@ Wire Wire Line
 	2400 4650 2750 4650
 Wire Wire Line
 	2400 5250 2750 5250
-Text Label 2450 5250 0    60   ~ 0
-FPD-
-Text Label 2450 4650 0    60   ~ 0
-FPD+
 Text Notes 650  4450 0    60   ~ 0
 USB pull lines connected to\nBANK0 on "gpio" sheet
 $Comp
@ -832,4 +828,8 @@ Wire Wire Line
 	2600 2850 2600 2900
 Wire Wire Line
 	2700 2750 2700 2900
+Text GLabel 2750 4650 2    60   Input ~ 0
+USB_FPGA_D+
+Text GLabel 2750 5250 2    60   Input ~ 0
+USB_FPGA_D-
 $EndSCHEMATC